From: Catalin Marinas Date: Thu, 14 Nov 2024 12:07:16 +0000 (+0000) Subject: Merge branches 'for-next/gcs', 'for-next/probes', 'for-next/asm-offsets', 'for-next... X-Git-Tag: v6.13-rc1~203^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5a4332062e9e71de8e78dc1b389d21e0dd44848b;p=thirdparty%2Fkernel%2Flinux.git Merge branches 'for-next/gcs', 'for-next/probes', 'for-next/asm-offsets', 'for-next/tlb', 'for-next/misc', 'for-next/mte', 'for-next/sysreg', 'for-next/stacktrace', 'for-next/hwcap3', 'for-next/kselftest', 'for-next/crc32', 'for-next/guest-cca', 'for-next/haft' and 'for-next/scs', remote-tracking branch 'arm64/for-next/perf' into for-next/core * arm64/for-next/perf: perf: Switch back to struct platform_driver::remove() perf: arm_pmuv3: Add support for Samsung Mongoose PMU dt-bindings: arm: pmu: Add Samsung Mongoose core compatible perf/dwc_pcie: Fix typos in event names perf/dwc_pcie: Add support for Ampere SoCs ARM: pmuv3: Add missing write_pmuacr() perf/marvell: Marvell PEM performance monitor support perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control perf/dwc_pcie: Convert the events with mixed case to lowercase perf/cxlpmu: Support missing events in 3.1 spec perf: imx_perf: add support for i.MX91 platform dt-bindings: perf: fsl-imx-ddr: Add i.MX91 compatible drivers perf: remove unused field pmu_node * for-next/gcs: (42 commits) : arm64 Guarded Control Stack user-space support kselftest/arm64: Fix missing printf() argument in gcs/gcs-stress.c arm64/gcs: Fix outdated ptrace documentation kselftest/arm64: Ensure stable names for GCS stress test results kselftest/arm64: Validate that GCS push and write permissions work kselftest/arm64: Enable GCS for the FP stress tests kselftest/arm64: Add a GCS stress test kselftest/arm64: Add GCS signal tests kselftest/arm64: Add test coverage for GCS mode locking kselftest/arm64: Add a GCS test program built with the system libc kselftest/arm64: Add very basic GCS test program kselftest/arm64: Always run signals tests with GCS enabled kselftest/arm64: Allow signals tests to specify an expected si_code kselftest/arm64: Add framework support for GCS to signal handling tests kselftest/arm64: Add GCS as a detected feature in the signal tests kselftest/arm64: Verify the GCS hwcap arm64: Add Kconfig for Guarded Control Stack (GCS) arm64/ptrace: Expose GCS via ptrace and core files arm64/signal: Expose GCS state in signal frames arm64/signal: Set up and restore the GCS context for signal handlers arm64/mm: Implement map_shadow_stack() ... * for-next/probes: : Various arm64 uprobes/kprobes cleanups arm64: insn: Simulate nop instruction for better uprobe performance arm64: probes: Remove probe_opcode_t arm64: probes: Cleanup kprobes endianness conversions arm64: probes: Move kprobes-specific fields arm64: probes: Fix uprobes for big-endian kernels arm64: probes: Fix simulate_ldr*_literal() arm64: probes: Remove broken LDR (literal) uprobe support * for-next/asm-offsets: : arm64 asm-offsets.c cleanup (remove unused offsets) arm64: asm-offsets: remove PREEMPT_DISABLE_OFFSET arm64: asm-offsets: remove DMA_{TO,FROM}_DEVICE arm64: asm-offsets: remove VM_EXEC and PAGE_SZ arm64: asm-offsets: remove MM_CONTEXT_ID arm64: asm-offsets: remove COMPAT_{RT_,SIGFRAME_REGS_OFFSET arm64: asm-offsets: remove VMA_VM_* arm64: asm-offsets: remove TSK_ACTIVE_MM * for-next/tlb: : TLB flushing optimisations arm64: optimize flush tlb kernel range arm64: tlbflush: add __flush_tlb_range_limit_excess() * for-next/misc: : Miscellaneous patches arm64: tls: Fix context-switching of tpidrro_el0 when kpti is enabled arm64/ptrace: Clarify documentation of VL configuration via ptrace acpi/arm64: remove unnecessary cast arm64/mm: Change protval as 'pteval_t' in map_range() arm64: uprobes: Optimize cache flushes for xol slot acpi/arm64: Adjust error handling procedure in gtdt_parse_timer_block() arm64: fix .data.rel.ro size assertion when CONFIG_LTO_CLANG arm64/ptdump: Test both PTE_TABLE_BIT and PTE_VALID for block mappings arm64/mm: Sanity check PTE address before runtime P4D/PUD folding arm64/mm: Drop setting PTE_TYPE_PAGE in pte_mkcont() ACPI: GTDT: Tighten the check for the array of platform timer structures arm64/fpsimd: Fix a typo arm64: Expose ID_AA64ISAR1_EL1.XS to sanitised feature consumers arm64: Return early when break handler is found on linked-list arm64/mm: Re-organize arch_make_huge_pte() arm64/mm: Drop _PROT_SECT_DEFAULT arm64: Add command-line override for ID_AA64MMFR0_EL1.ECV arm64: head: Drop SWAPPER_TABLE_SHIFT arm64: cpufeature: add POE to cpucap_is_possible() arm64/mm: Change pgattr_change_is_safe() arguments as pteval_t * for-next/mte: : Various MTE improvements selftests: arm64: add hugetlb mte tests hugetlb: arm64: add mte support * for-next/sysreg: : arm64 sysreg updates arm64/sysreg: Update ID_AA64MMFR1_EL1 to DDI0601 2024-09 * for-next/stacktrace: : arm64 stacktrace improvements arm64: preserve pt_regs::stackframe during exec*() arm64: stacktrace: unwind exception boundaries arm64: stacktrace: split unwind_consume_stack() arm64: stacktrace: report recovered PCs arm64: stacktrace: report source of unwind data arm64: stacktrace: move dump_backtrace() to kunwind_stack_walk() arm64: use a common struct frame_record arm64: pt_regs: swap 'unused' and 'pmr' fields arm64: pt_regs: rename "pmr_save" -> "pmr" arm64: pt_regs: remove stale big-endian layout arm64: pt_regs: assert pt_regs is a multiple of 16 bytes * for-next/hwcap3: : Add AT_HWCAP3 support for arm64 (also wire up AT_HWCAP4) arm64: Support AT_HWCAP3 binfmt_elf: Wire up AT_HWCAP3 at AT_HWCAP4 * for-next/kselftest: (30 commits) : arm64 kselftest fixes/cleanups kselftest/arm64: Try harder to generate different keys during PAC tests kselftest/arm64: Don't leak pipe fds in pac.exec_sign_all() kselftest/arm64: Corrupt P0 in the irritator when testing SSVE kselftest/arm64: Add FPMR coverage to fp-ptrace kselftest/arm64: Expand the set of ZA writes fp-ptrace does kselftets/arm64: Use flag bits for features in fp-ptrace assembler code kselftest/arm64: Enable build of PAC tests with LLVM=1 kselftest/arm64: Check that SVCR is 0 in signal handlers kselftest/arm64: Fix printf() compiler warnings in the arm64 syscall-abi.c tests kselftest/arm64: Fix printf() warning in the arm64 MTE prctl() test kselftest/arm64: Fix printf() compiler warnings in the arm64 fp tests kselftest/arm64: Fix build with stricter assemblers kselftest/arm64: Test signal handler state modification in fp-stress kselftest/arm64: Provide a SIGUSR1 handler in the kernel mode FP stress test kselftest/arm64: Implement irritators for ZA and ZT kselftest/arm64: Remove unused ADRs from irritator handlers kselftest/arm64: Correct misleading comments on fp-stress irritators kselftest/arm64: Poll less often while waiting for fp-stress children kselftest/arm64: Increase frequency of signal delivery in fp-stress kselftest/arm64: Fix encoding for SVE B16B16 test ... * for-next/crc32: : Optimise CRC32 using PMULL instructions arm64/crc32: Implement 4-way interleave using PMULL arm64/crc32: Reorganize bit/byte ordering macros arm64/lib: Handle CRC-32 alternative in C code * for-next/guest-cca: : Support for running Linux as a guest in Arm CCA arm64: Document Arm Confidential Compute virt: arm-cca-guest: TSM_REPORT support for realms arm64: Enable memory encrypt for Realms arm64: mm: Avoid TLBI when marking pages as valid arm64: Enforce bounce buffers for realm DMA efi: arm64: Map Device with Prot Shared arm64: rsi: Map unprotected MMIO as decrypted arm64: rsi: Add support for checking whether an MMIO is protected arm64: realm: Query IPA size from the RMM arm64: Detect if in a realm and set RIPAS RAM arm64: rsi: Add RSI definitions * for-next/haft: : Support for arm64 FEAT_HAFT arm64: pgtable: Warn unexpected pmdp_test_and_clear_young() arm64: Enable ARCH_HAS_NONLEAF_PMD_YOUNG arm64: Add support for FEAT_HAFT arm64: setup: name 'tcr2' register arm64/sysreg: Update ID_AA64MMFR1_EL1 register * for-next/scs: : Dynamic shadow call stack fixes arm64/scs: Drop unused prototype __pi_scs_patch_vmlinux() arm64/scs: Deal with 64-bit relative offsets in FDE frames arm64/scs: Fix handling of DWARF augmentation data in CIE/FDE frames --- 5a4332062e9e71de8e78dc1b389d21e0dd44848b diff --cc arch/arm64/Kconfig index fd9df6dcc5937,dcb12f041c134,fd9df6dcc5937,3e29b44d2d7bd,3e29b44d2d7bd,3e29b44d2d7bd,3e29b44d2d7bd,3e29b44d2d7bd,3e29b44d2d7bd,3e29b44d2d7bd,3e29b44d2d7bd,3e29b44d2d7bd,ccea9c22d6dff,d2ca7b6c6f859,fd9df6dcc5937..5afd028116c93 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@@@@@@@@@@@@@@@ -2177,8 -2176,29 -2177,8 -2176,8 -2176,8 -2176,8 -2176,8 -2176,8 -2176,8 -2176,8 -2176,8 -2176,8 -2179,8 -2177,23 -2177,8 +2181,44 @@@@@@@@@@@@@@@@ config ARCH_PKEY_BIT int default 3 +++++++++++++ +config ARM64_HAFT +++++++++++++ + bool "Support for Hardware managed Access Flag for Table Descriptors" +++++++++++++ + depends on ARM64_HW_AFDBM +++++++++++++ + default y +++++++++++++ + help +++++++++++++ + The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access +++++++++++++ + Flag for Table descriptors. When enabled an architectural executed +++++++++++++ + memory access will update the Access Flag in each Table descriptor +++++++++++++ + which is accessed during the translation table walk and for which +++++++++++++ + the Access Flag is 0. The Access Flag of the Table descriptor use +++++++++++++ + the same bit of PTE_AF. +++++++++++++ + +++++++++++++ + The feature will only be enabled if all the CPUs in the system +++++++++++++ + support this feature. If unsure, say Y. +++++++++++++ + endmenu # "ARMv8.9 architectural features" + +++++++++++++menu "v9.4 architectural features" + +++++++++++++ + +++++++++++++config ARM64_GCS + +++++++++++++ bool "Enable support for Guarded Control Stack (GCS)" + +++++++++++++ default y + +++++++++++++ select ARCH_HAS_USER_SHADOW_STACK + +++++++++++++ select ARCH_USES_HIGH_VMA_FLAGS + +++++++++++++ depends on !UPROBES + +++++++++++++ help + +++++++++++++ Guarded Control Stack (GCS) provides support for a separate + +++++++++++++ stack with restricted access which contains only return + +++++++++++++ addresses. This can be used to harden against some attacks + +++++++++++++ by comparing return address used by the program with what is + +++++++++++++ stored in the GCS, and may also be used to efficiently obtain + +++++++++++++ the call stack for applications such as profiling. + +++++++++++++ + +++++++++++++ The feature is detected at runtime, and will remain disabled + +++++++++++++ if the system does not implement the feature. + +++++++++++++ + +++++++++++++endmenu # "v9.4 architectural features" + +++++++++++++ config ARM64_SVE bool "ARM Scalable Vector Extension support" default y diff --cc arch/arm64/include/asm/cpufeature.h index 3d261cc123c1e,69470795f5d2a,3d261cc123c1e,3d261cc123c1e,3d261cc123c1e,4b6bc0bac9b93,3d261cc123c1e,3d261cc123c1e,3d261cc123c1e,38e7d1a44ea38,3d261cc123c1e,3d261cc123c1e,3d261cc123c1e,ed8c784ca082c,3d261cc123c1e..3d63c20ccefcd --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@@@@@@@@@@@@@@@ -834,10 -834,16 -834,10 -834,10 -834,10 -834,9 -834,10 -834,10 -834,10 -835,10 -834,10 -834,10 -834,10 -834,16 -834,10 +835,21 @@@@@@@@@@@@@@@@ static inline bool system_supports_lpa2 static inline bool system_supports_poe(void) { ----- --------- return IS_ENABLED(CONFIG_ARM64_POE) && ----- --------- alternative_has_cap_unlikely(ARM64_HAS_S1POE); +++++ +++++++++ return alternative_has_cap_unlikely(ARM64_HAS_S1POE); + +++ +++++++++} + +++ +++++++++ + +++++++++++++static inline bool system_supports_gcs(void) + +++++++++++++{ + +++++++++++++ return IS_ENABLED(CONFIG_ARM64_GCS) && + +++++++++++++ alternative_has_cap_unlikely(ARM64_HAS_GCS); + +++++++++++ +} + +++++++++++ + +++++++++++++ +static inline bool system_supports_haft(void) +++++++++++++ +{ +++++++++++++ + return IS_ENABLED(CONFIG_ARM64_HAFT) && +++++++++++++ + cpus_have_final_cap(ARM64_HAFT); + + } + + int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); bool try_emulate_mrs(struct pt_regs *regs, u32 isn); diff --cc arch/arm64/include/asm/processor.h index 1438424f00643,37fefdc3d3a39,1438424f00643,1438424f00643,1438424f00643,1438424f00643,1438424f00643,1438424f00643,e277105fb87a2,1438424f00643,1438424f00643,1438424f00643,1438424f00643,1438424f00643,1438424f00643..1bf1a3b16e886 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@@@@@@@@@@@@@@@ -285,15 -292,15 -285,15 -285,15 -285,15 -285,15 -285,15 -285,15 -285,38 -285,15 -285,15 -285,15 -285,15 -285,15 -285,15 +292,38 @@@@@@@@@@@@@@@@ void tls_preserve_current_state(void) .fpsimd_cpu = NR_CPUS, \ } -------- ------static inline void start_thread_common(struct pt_regs *regs, unsigned long pc) ++++++++ ++++++static inline void start_thread_common(struct pt_regs *regs, unsigned long pc, ++++++++ ++++++ unsigned long pstate) { -------- ------ s32 previous_syscall = regs->syscallno; -------- ------ memset(regs, 0, sizeof(*regs)); -------- ------ regs->syscallno = previous_syscall; -------- ------ regs->pc = pc; ++++++++ ++++++ /* ++++++++ ++++++ * Ensure all GPRs are zeroed, and initialize PC + PSTATE. ++++++++ ++++++ * The SP (or compat SP) will be initialized later. ++++++++ ++++++ */ ++++++++ ++++++ regs->user_regs = (struct user_pt_regs) { ++++++++ ++++++ .pc = pc, ++++++++ ++++++ .pstate = pstate, ++++++++ ++++++ }; + ++++++++ ++++++ /* ++++++++ ++++++ * To allow the syscalls:sys_exit_execve tracepoint we need to preserve ++++++++ ++++++ * syscallno, but do not need orig_x0 or the original GPRs. ++++++++ ++++++ */ ++++++++ ++++++ regs->orig_x0 = 0; + ++++++ ++++++ ++++++++ ++++++ /* ++++++++ ++++++ * An exec from a kernel thread won't have an existing PMR value. ++++++++ ++++++ */ if (system_uses_irq_prio_masking()) -------- ------ regs->pmr_save = GIC_PRIO_IRQON; ++++++++ ++++++ regs->pmr = GIC_PRIO_IRQON; ++++++++ ++++++ ++++++++ ++++++ /* ++++++++ ++++++ * The pt_regs::stackframe field must remain valid throughout this ++++++++ ++++++ * function as a stacktrace can be taken at any time. Any user or ++++++++ ++++++ * kernel task should have a valid final frame. ++++++++ ++++++ */ ++++++++ ++++++ WARN_ON_ONCE(regs->stackframe.record.fp != 0); ++++++++ ++++++ WARN_ON_ONCE(regs->stackframe.record.lr != 0); ++++++++ ++++++ WARN_ON_ONCE(regs->stackframe.type != FRAME_META_TYPE_FINAL); } static inline void start_thread(struct pt_regs *regs, unsigned long pc,