From: Greg Kroah-Hartman Date: Mon, 19 Jan 2015 13:28:00 +0000 (+0800) Subject: 3.18-stable patches X-Git-Tag: v3.10.66~52 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5a82cf7eab10f7bbbfcc287ff88e52d4449aac44;p=thirdparty%2Fkernel%2Fstable-queue.git 3.18-stable patches added patches: arc-move-peripherals-to-match-model-to-fpga.patch cxl-add-timeout-to-process-element-commands.patch cxl-change-contexts_lock-to-a-mutex-to-fix-sleep-while-atomic-bug.patch cxl-unmap-mmio-regions-when-detaching-a-context.patch drm-i915-disable-psmi-sleep-messages-on-all-rings-around-context-switches.patch drm-i915-don-t-call-intel_prepare_page_flip-multiple-times-on-gen2-4.patch drm-i915-force-the-cs-stall-for-invalidate-flushes.patch drm-i915-invalidate-media-caches-on-gen7.patch drm-irq-bug_on-warn_on.patch drm-nv4c-mc-disable-msi.patch --- diff --git a/queue-3.18/arc-move-peripherals-to-match-model-to-fpga.patch b/queue-3.18/arc-move-peripherals-to-match-model-to-fpga.patch new file mode 100644 index 00000000000..29638650900 --- /dev/null +++ b/queue-3.18/arc-move-peripherals-to-match-model-to-fpga.patch @@ -0,0 +1,69 @@ +From e8ef060b37c2d3cc5fd0c0edbe4e42ec1cb9768b Mon Sep 17 00:00:00 2001 +From: Vineet Gupta +Date: Wed, 1 Oct 2014 14:28:36 +0530 +Subject: ARC: [nsimosci] move peripherals to match model to FPGA + +From: Vineet Gupta + +commit e8ef060b37c2d3cc5fd0c0edbe4e42ec1cb9768b upstream. + +This allows the sdplite/Zebu images to run on OSCI simulation platform + +Signed-off-by: Vineet Gupta +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arc/boot/dts/nsimosci.dts | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/arch/arc/boot/dts/nsimosci.dts ++++ b/arch/arc/boot/dts/nsimosci.dts +@@ -20,7 +20,7 @@ + /* this is for console on PGU */ + /* bootargs = "console=tty0 consoleblank=0"; */ + /* this is for console on serial */ +- bootargs = "earlycon=uart8250,mmio32,0xc0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug"; ++ bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug"; + }; + + aliases { +@@ -41,9 +41,9 @@ + #interrupt-cells = <1>; + }; + +- uart0: serial@c0000000 { ++ uart0: serial@f0000000 { + compatible = "ns8250"; +- reg = <0xc0000000 0x2000>; ++ reg = <0xf0000000 0x2000>; + interrupts = <11>; + clock-frequency = <3686400>; + baud = <115200>; +@@ -52,21 +52,21 @@ + no-loopback-test = <1>; + }; + +- pgu0: pgu@c9000000 { ++ pgu0: pgu@f9000000 { + compatible = "snps,arcpgufb"; +- reg = <0xc9000000 0x400>; ++ reg = <0xf9000000 0x400>; + }; + +- ps2: ps2@c9001000 { ++ ps2: ps2@f9001000 { + compatible = "snps,arc_ps2"; +- reg = <0xc9000400 0x14>; ++ reg = <0xf9000400 0x14>; + interrupts = <13>; + interrupt-names = "arc_ps2_irq"; + }; + +- eth0: ethernet@c0003000 { ++ eth0: ethernet@f0003000 { + compatible = "snps,oscilan"; +- reg = <0xc0003000 0x44>; ++ reg = <0xf0003000 0x44>; + interrupts = <7>, <8>; + interrupt-names = "rx", "tx"; + }; diff --git a/queue-3.18/cxl-add-timeout-to-process-element-commands.patch b/queue-3.18/cxl-add-timeout-to-process-element-commands.patch new file mode 100644 index 00000000000..43000e26045 --- /dev/null +++ b/queue-3.18/cxl-add-timeout-to-process-element-commands.patch @@ -0,0 +1,46 @@ +From a98e6e9f4e0224d85b4d951edc44af16dfe6094a Mon Sep 17 00:00:00 2001 +From: Ian Munsie +Date: Mon, 8 Dec 2014 19:17:56 +1100 +Subject: cxl: Add timeout to process element commands + +From: Ian Munsie + +commit a98e6e9f4e0224d85b4d951edc44af16dfe6094a upstream. + +In the event that something goes wrong in the hardware and it is unable +to complete a process element comment we would end up polling forever, +effectively making the associated process unkillable. + +This patch adds a timeout to the process element command code path, so +that we will give up if the hardware does not respond in a reasonable +time. + +Signed-off-by: Ian Munsie +Signed-off-by: Michael Ellerman +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/misc/cxl/native.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/misc/cxl/native.c ++++ b/drivers/misc/cxl/native.c +@@ -277,6 +277,7 @@ static int do_process_element_cmd(struct + u64 cmd, u64 pe_state) + { + u64 state; ++ unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); + + WARN_ON(!ctx->afu->enabled); + +@@ -286,6 +287,10 @@ static int do_process_element_cmd(struct + smp_mb(); + cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); + while (1) { ++ if (time_after_eq(jiffies, timeout)) { ++ dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); ++ return -EBUSY; ++ } + state = be64_to_cpup(ctx->afu->sw_command_status); + if (state == ~0ULL) { + pr_err("cxl: Error adding process element to AFU\n"); diff --git a/queue-3.18/cxl-change-contexts_lock-to-a-mutex-to-fix-sleep-while-atomic-bug.patch b/queue-3.18/cxl-change-contexts_lock-to-a-mutex-to-fix-sleep-while-atomic-bug.patch new file mode 100644 index 00000000000..a30cfc2d1f0 --- /dev/null +++ b/queue-3.18/cxl-change-contexts_lock-to-a-mutex-to-fix-sleep-while-atomic-bug.patch @@ -0,0 +1,168 @@ +From ee41d11d53c8fc4968f0816504651541d606cf40 Mon Sep 17 00:00:00 2001 +From: Ian Munsie +Date: Mon, 8 Dec 2014 19:17:55 +1100 +Subject: cxl: Change contexts_lock to a mutex to fix sleep while atomic bug + +From: Ian Munsie + +commit ee41d11d53c8fc4968f0816504651541d606cf40 upstream. + +We had a known sleep while atomic bug if a CXL device was forcefully +unbound while it was in use. This could occur as a result of EEH, or +manually induced with something like this while the device was in use: + +echo 0000:01:00.0 > /sys/bus/pci/drivers/cxl-pci/unbind + +The issue was that in this code path we iterated over each context and +forcefully detached it with the contexts_lock spin lock held, however +the detach also needed to take the spu_mutex, and call schedule. + +This patch changes the contexts_lock to a mutex so that we are not in +atomic context while doing the detach, thereby avoiding the sleep while +atomic. + +Also delete the related TODO comment, which suggested an alternate +solution which turned out to not be workable. + +Signed-off-by: Ian Munsie +Signed-off-by: Michael Ellerman +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/misc/cxl/context.c | 15 ++++++++------- + drivers/misc/cxl/cxl.h | 2 +- + drivers/misc/cxl/native.c | 7 ------- + drivers/misc/cxl/pci.c | 2 +- + drivers/misc/cxl/sysfs.c | 10 +++++----- + 5 files changed, 15 insertions(+), 21 deletions(-) + +--- a/drivers/misc/cxl/context.c ++++ b/drivers/misc/cxl/context.c +@@ -82,12 +82,12 @@ int cxl_context_init(struct cxl_context + * Allocating IDR! We better make sure everything's setup that + * dereferences from it. + */ ++ mutex_lock(&afu->contexts_lock); + idr_preload(GFP_KERNEL); +- spin_lock(&afu->contexts_lock); + i = idr_alloc(&ctx->afu->contexts_idr, ctx, 0, + ctx->afu->num_procs, GFP_NOWAIT); +- spin_unlock(&afu->contexts_lock); + idr_preload_end(); ++ mutex_unlock(&afu->contexts_lock); + if (i < 0) + return i; + +@@ -168,21 +168,22 @@ void cxl_context_detach_all(struct cxl_a + struct cxl_context *ctx; + int tmp; + +- rcu_read_lock(); +- idr_for_each_entry(&afu->contexts_idr, ctx, tmp) ++ mutex_lock(&afu->contexts_lock); ++ idr_for_each_entry(&afu->contexts_idr, ctx, tmp) { + /* + * Anything done in here needs to be setup before the IDR is + * created and torn down after the IDR removed + */ + __detach_context(ctx); +- rcu_read_unlock(); ++ } ++ mutex_unlock(&afu->contexts_lock); + } + + void cxl_context_free(struct cxl_context *ctx) + { +- spin_lock(&ctx->afu->contexts_lock); ++ mutex_lock(&ctx->afu->contexts_lock); + idr_remove(&ctx->afu->contexts_idr, ctx->pe); +- spin_unlock(&ctx->afu->contexts_lock); ++ mutex_unlock(&ctx->afu->contexts_lock); + synchronize_rcu(); + + free_page((u64)ctx->sstp); +--- a/drivers/misc/cxl/cxl.h ++++ b/drivers/misc/cxl/cxl.h +@@ -349,7 +349,7 @@ struct cxl_afu { + struct device *chardev_s, *chardev_m, *chardev_d; + struct idr contexts_idr; + struct dentry *debugfs; +- spinlock_t contexts_lock; ++ struct mutex contexts_lock; + struct mutex spa_mutex; + spinlock_t afu_cntl_lock; + +--- a/drivers/misc/cxl/native.c ++++ b/drivers/misc/cxl/native.c +@@ -610,13 +610,6 @@ static inline int detach_process_native_ + return 0; + } + +-/* +- * TODO: handle case when this is called inside a rcu_read_lock() which may +- * happen when we unbind the driver (ie. cxl_context_detach_all()) . Terminate +- * & remove use a mutex lock and schedule which will not good with lock held. +- * May need to write do_process_element_cmd() that handles outstanding page +- * faults synchronously. +- */ + static inline int detach_process_native_afu_directed(struct cxl_context *ctx) + { + if (!ctx->pe_inserted) +--- a/drivers/misc/cxl/pci.c ++++ b/drivers/misc/cxl/pci.c +@@ -502,7 +502,7 @@ static struct cxl_afu *cxl_alloc_afu(str + afu->dev.release = cxl_release_afu; + afu->slice = slice; + idr_init(&afu->contexts_idr); +- spin_lock_init(&afu->contexts_lock); ++ mutex_init(&afu->contexts_lock); + spin_lock_init(&afu->afu_cntl_lock); + mutex_init(&afu->spa_mutex); + +--- a/drivers/misc/cxl/sysfs.c ++++ b/drivers/misc/cxl/sysfs.c +@@ -121,7 +121,7 @@ static ssize_t reset_store_afu(struct de + int rc; + + /* Not safe to reset if it is currently in use */ +- spin_lock(&afu->contexts_lock); ++ mutex_lock(&afu->contexts_lock); + if (!idr_is_empty(&afu->contexts_idr)) { + rc = -EBUSY; + goto err; +@@ -132,7 +132,7 @@ static ssize_t reset_store_afu(struct de + + rc = count; + err: +- spin_unlock(&afu->contexts_lock); ++ mutex_unlock(&afu->contexts_lock); + return rc; + } + +@@ -247,7 +247,7 @@ static ssize_t mode_store(struct device + int rc = -EBUSY; + + /* can't change this if we have a user */ +- spin_lock(&afu->contexts_lock); ++ mutex_lock(&afu->contexts_lock); + if (!idr_is_empty(&afu->contexts_idr)) + goto err; + +@@ -271,7 +271,7 @@ static ssize_t mode_store(struct device + afu->current_mode = 0; + afu->num_procs = 0; + +- spin_unlock(&afu->contexts_lock); ++ mutex_unlock(&afu->contexts_lock); + + if ((rc = _cxl_afu_deactivate_mode(afu, old_mode))) + return rc; +@@ -280,7 +280,7 @@ static ssize_t mode_store(struct device + + return count; + err: +- spin_unlock(&afu->contexts_lock); ++ mutex_unlock(&afu->contexts_lock); + return rc; + } + diff --git a/queue-3.18/cxl-unmap-mmio-regions-when-detaching-a-context.patch b/queue-3.18/cxl-unmap-mmio-regions-when-detaching-a-context.patch new file mode 100644 index 00000000000..432d68e3b3f --- /dev/null +++ b/queue-3.18/cxl-unmap-mmio-regions-when-detaching-a-context.patch @@ -0,0 +1,106 @@ +From b123429e6a9e8d03aacf888d23262835f0081448 Mon Sep 17 00:00:00 2001 +From: Ian Munsie +Date: Mon, 8 Dec 2014 19:18:01 +1100 +Subject: cxl: Unmap MMIO regions when detaching a context + +From: Ian Munsie + +commit b123429e6a9e8d03aacf888d23262835f0081448 upstream. + +If we need to force detach a context (e.g. due to EEH or simply force +unbinding the driver) we should prevent the userspace contexts from +being able to access the Problem State Area MMIO region further, which +they may have mapped with mmap(). + +This patch unmaps any mapped MMIO regions when detaching a userspace +context. + +Signed-off-by: Ian Munsie +Signed-off-by: Michael Ellerman +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/misc/cxl/context.c | 11 ++++++++++- + drivers/misc/cxl/cxl.h | 7 ++++++- + drivers/misc/cxl/file.c | 6 +++++- + 3 files changed, 21 insertions(+), 3 deletions(-) + +--- a/drivers/misc/cxl/context.c ++++ b/drivers/misc/cxl/context.c +@@ -34,7 +34,8 @@ struct cxl_context *cxl_context_alloc(vo + /* + * Initialises a CXL context. + */ +-int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master) ++int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master, ++ struct address_space *mapping) + { + int i; + +@@ -42,6 +43,8 @@ int cxl_context_init(struct cxl_context + ctx->afu = afu; + ctx->master = master; + ctx->pid = NULL; /* Set in start work ioctl */ ++ mutex_init(&ctx->mapping_lock); ++ ctx->mapping = mapping; + + /* + * Allocate the segment table before we put it in the IDR so that we +@@ -147,6 +150,12 @@ static void __detach_context(struct cxl_ + afu_release_irqs(ctx); + flush_work(&ctx->fault_work); /* Only needed for dedicated process */ + wake_up_all(&ctx->wq); ++ ++ /* Release Problem State Area mapping */ ++ mutex_lock(&ctx->mapping_lock); ++ if (ctx->mapping) ++ unmap_mapping_range(ctx->mapping, 0, 0, 1); ++ mutex_unlock(&ctx->mapping_lock); + } + + /* +--- a/drivers/misc/cxl/cxl.h ++++ b/drivers/misc/cxl/cxl.h +@@ -390,6 +390,10 @@ struct cxl_context { + phys_addr_t psn_phys; + u64 psn_size; + ++ /* Used to unmap any mmaps when force detaching */ ++ struct address_space *mapping; ++ struct mutex mapping_lock; ++ + spinlock_t sste_lock; /* Protects segment table entries */ + struct cxl_sste *sstp; + u64 sstp0, sstp1; +@@ -592,7 +596,8 @@ int cxl_alloc_sst(struct cxl_context *ct + void init_cxl_native(void); + + struct cxl_context *cxl_context_alloc(void); +-int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master); ++int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master, ++ struct address_space *mapping); + void cxl_context_free(struct cxl_context *ctx); + int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma); + +--- a/drivers/misc/cxl/file.c ++++ b/drivers/misc/cxl/file.c +@@ -77,7 +77,7 @@ static int __afu_open(struct inode *inod + goto err_put_afu; + } + +- if ((rc = cxl_context_init(ctx, afu, master))) ++ if ((rc = cxl_context_init(ctx, afu, master, inode->i_mapping))) + goto err_put_afu; + + pr_devel("afu_open pe: %i\n", ctx->pe); +@@ -113,6 +113,10 @@ static int afu_release(struct inode *ino + __func__, ctx->pe); + cxl_context_detach(ctx); + ++ mutex_lock(&ctx->mapping_lock); ++ ctx->mapping = NULL; ++ mutex_unlock(&ctx->mapping_lock); ++ + put_device(&ctx->afu->dev); + + /* diff --git a/queue-3.18/drm-i915-disable-psmi-sleep-messages-on-all-rings-around-context-switches.patch b/queue-3.18/drm-i915-disable-psmi-sleep-messages-on-all-rings-around-context-switches.patch new file mode 100644 index 00000000000..b46bc2812ed --- /dev/null +++ b/queue-3.18/drm-i915-disable-psmi-sleep-messages-on-all-rings-around-context-switches.patch @@ -0,0 +1,153 @@ +From 2c550183476dfa25641309ae9a28d30feed14379 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 16 Dec 2014 10:02:27 +0000 +Subject: drm/i915: Disable PSMI sleep messages on all rings around context switches +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit 2c550183476dfa25641309ae9a28d30feed14379 upstream. + +There exists a current workaround to prevent a hang on context switch +should the ring go to sleep in the middle of the restore, +WaProgramMiArbOnOffAroundMiSetContext (applicable to all gen7+). In +spite of disabling arbitration (which prevents the ring from powering +down during the critical section) we were still hitting hangs that had +the hallmarks of the known erratum. That is we are still seeing hangs +"on the last instruction in the context restore". By comparing -nightly +(broken) with requests (working), we were able to deduce that it was the +semaphore LRI cross-talk that reproduced the original failure. The key +was that requests implemented deferred semaphore signalling, and +disabling that, i.e. emitting the semaphore signal to every other ring +after every batch restored the frequent hang. Explicitly disabling PSMI +sleep on the RCS ring was insufficient, all the rings had to be awake to +prevent the hangs. Fortunately, we can reduce the wakelock to the +MI_SET_CONTEXT operation itself, and so should be able to limit the extra +power implications. + +Since the MI_ARB_ON_OFF workaround is listed for all gen7 and above +products, we should apply this extra hammer for all of the same +platforms despite so far that we have only been able to reproduce the +hang on certain ivb and hsw models. The last question is whether we want +to always use the extra hammer or only when we know semaphores are in +operation. At the moment, we only use LRI on non-RCS rings for +semaphores, but that may change in the future with the possibility of +reintroducing this bug under subtle conditions. + +v2: Make it explicit that the PSMI LRI are an extension to the original +workaround for the other rings. +v3: Bikeshedding variable names and whitespacing + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80660 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83677 +Cc: Simon Farnsworth +Cc: Daniel Vetter +Cc: Ville Syrjälä +Signed-off-by: Chris Wilson +Tested-by: Peter Frühberger +Reviewed-by: Daniel Vetter +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_gem_context.c | 48 ++++++++++++++++++++++++++------ + drivers/gpu/drm/i915/i915_reg.h | 2 + + 2 files changed, 42 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_gem_context.c ++++ b/drivers/gpu/drm/i915/i915_gem_context.c +@@ -468,7 +468,12 @@ mi_set_context(struct intel_engine_cs *r + u32 hw_flags) + { + u32 flags = hw_flags | MI_MM_SPACE_GTT; +- int ret; ++ const int num_rings = ++ /* Use an extended w/a on ivb+ if signalling from other rings */ ++ i915_semaphore_is_enabled(ring->dev) ? ++ hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 : ++ 0; ++ int len, i, ret; + + /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB + * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value +@@ -485,15 +490,31 @@ mi_set_context(struct intel_engine_cs *r + if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8) + flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN); + +- ret = intel_ring_begin(ring, 6); ++ ++ len = 4; ++ if (INTEL_INFO(ring->dev)->gen >= 7) ++ len += 2 + (num_rings ? 4*num_rings + 2 : 0); ++ ++ ret = intel_ring_begin(ring, len); + if (ret) + return ret; + + /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ +- if (INTEL_INFO(ring->dev)->gen >= 7) ++ if (INTEL_INFO(ring->dev)->gen >= 7) { + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); +- else +- intel_ring_emit(ring, MI_NOOP); ++ if (num_rings) { ++ struct intel_engine_cs *signaller; ++ ++ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); ++ for_each_ring(signaller, to_i915(ring->dev), i) { ++ if (signaller == ring) ++ continue; ++ ++ intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); ++ intel_ring_emit(ring, _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); ++ } ++ } ++ } + + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_SET_CONTEXT); +@@ -505,10 +526,21 @@ mi_set_context(struct intel_engine_cs *r + */ + intel_ring_emit(ring, MI_NOOP); + +- if (INTEL_INFO(ring->dev)->gen >= 7) ++ if (INTEL_INFO(ring->dev)->gen >= 7) { ++ if (num_rings) { ++ struct intel_engine_cs *signaller; ++ ++ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings)); ++ for_each_ring(signaller, to_i915(ring->dev), i) { ++ if (signaller == ring) ++ continue; ++ ++ intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base)); ++ intel_ring_emit(ring, _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); ++ } ++ } + intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); +- else +- intel_ring_emit(ring, MI_NOOP); ++ } + + intel_ring_advance(ring); + +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -1073,6 +1073,7 @@ enum punit_power_well { + #define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE)) + #define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE)) + #define GEN6_NOSYNC 0 ++#define RING_PSMI_CTL(base) ((base)+0x50) + #define RING_MAX_IDLE(base) ((base)+0x54) + #define RING_HWS_PGA(base) ((base)+0x80) + #define RING_HWS_PGA_GEN6(base) ((base)+0x2080) +@@ -1403,6 +1404,7 @@ enum punit_power_well { + #define GEN6_BLITTER_FBC_NOTIFY (1<<3) + + #define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050 ++#define GEN6_PSMI_SLEEP_MSG_DISABLE (1 << 0) + #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) + #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) + diff --git a/queue-3.18/drm-i915-don-t-call-intel_prepare_page_flip-multiple-times-on-gen2-4.patch b/queue-3.18/drm-i915-don-t-call-intel_prepare_page_flip-multiple-times-on-gen2-4.patch new file mode 100644 index 00000000000..6989888197d --- /dev/null +++ b/queue-3.18/drm-i915-don-t-call-intel_prepare_page_flip-multiple-times-on-gen2-4.patch @@ -0,0 +1,84 @@ +From 7d47559ee84b3ac206aa9e675606fafcd7c0b500 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Wed, 17 Dec 2014 23:08:03 +0200 +Subject: drm/i915: Don't call intel_prepare_page_flip() multiple times on gen2-4 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= + +commit 7d47559ee84b3ac206aa9e675606fafcd7c0b500 upstream. + +The flip stall detector kicks in when pending>=INTEL_FLIP_COMPLETE. That +means if we first call intel_prepare_page_flip() but don't call +intel_finish_page_flip(), the next stall check will erroneosly think +the page flip was somehow stuck. + +With enough debug spew emitted from the interrupt handler my 830 hangs +when this happens. My theory is that the previous vblank interrupt gets +sufficiently delayed that the handler will see the pending bit set in +IIR, but ISR still has the bit set as well (ie. the flip was processed +by CS but didn't complete yet). In this case the handler will proceed +to call intel_check_page_flip() immediately after +intel_prepare_page_flip(). It then tries to print a backtrace for the +stuck flip WARN, which apparetly results in way too much debug spew +delaying interrupt processing further. That then seems to cause an +endless loop in the interrupt handler, and the machine is dead until +the watchdog kicks in and reboots. At least limiting the number of +iterations of the loop in the interrupt handler also prevented the +hang. + +So it seems better to not call intel_prepare_page_flip() without +immediately calling intel_finish_page_flip(). The IIR/ISR trickery +avoids races here so this is a perfectly safe thing to do. + +v2: Fix typo in commit message (checkpatch) + +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=88381 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85888 +Reviewed-by: Chris Wilson +Signed-off-by: Ville Syrjälä +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_irq.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/i915/i915_irq.c ++++ b/drivers/gpu/drm/i915/i915_irq.c +@@ -4022,8 +4022,6 @@ static bool i8xx_handle_vblank(struct dr + if ((iir & flip_pending) == 0) + goto check_page_flip; + +- intel_prepare_page_flip(dev, plane); +- + /* We detect FlipDone by looking for the change in PendingFlip from '1' + * to '0' on the following vblank, i.e. IIR has the Pendingflip + * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence +@@ -4033,6 +4031,7 @@ static bool i8xx_handle_vblank(struct dr + if (I915_READ16(ISR) & flip_pending) + goto check_page_flip; + ++ intel_prepare_page_flip(dev, plane); + intel_finish_page_flip(dev, pipe); + return true; + +@@ -4210,8 +4209,6 @@ static bool i915_handle_vblank(struct dr + if ((iir & flip_pending) == 0) + goto check_page_flip; + +- intel_prepare_page_flip(dev, plane); +- + /* We detect FlipDone by looking for the change in PendingFlip from '1' + * to '0' on the following vblank, i.e. IIR has the Pendingflip + * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence +@@ -4221,6 +4218,7 @@ static bool i915_handle_vblank(struct dr + if (I915_READ(ISR) & flip_pending) + goto check_page_flip; + ++ intel_prepare_page_flip(dev, plane); + intel_finish_page_flip(dev, pipe); + return true; + diff --git a/queue-3.18/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch b/queue-3.18/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch new file mode 100644 index 00000000000..fac97d4983e --- /dev/null +++ b/queue-3.18/drm-i915-force-the-cs-stall-for-invalidate-flushes.patch @@ -0,0 +1,40 @@ +From add284a3a2481e759d6bec35f6444c32c8ddc383 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 16 Dec 2014 08:44:32 +0000 +Subject: drm/i915: Force the CS stall for invalidate flushes +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit add284a3a2481e759d6bec35f6444c32c8ddc383 upstream. + +In order to act as a full command barrier by itself, we need to tell the +pipecontrol to actually stall the command streamer while the flush runs. +We require the full command barrier before operations like +MI_SET_CONTEXT, which currently rely on a prior invalidate flush. + +References: https://bugs.freedesktop.org/show_bug.cgi?id=83677 +Cc: Simon Farnsworth +Cc: Daniel Vetter +Cc: Ville Syrjälä +Signed-off-by: Chris Wilson +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_ringbuffer.c ++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c +@@ -369,6 +369,8 @@ gen7_render_ring_flush(struct intel_engi + flags |= PIPE_CONTROL_QW_WRITE; + flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; + ++ flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; ++ + /* Workaround: we must issue a pipe_control with CS-stall bit + * set before a pipe_control command that has the state cache + * invalidate bit set. */ diff --git a/queue-3.18/drm-i915-invalidate-media-caches-on-gen7.patch b/queue-3.18/drm-i915-invalidate-media-caches-on-gen7.patch new file mode 100644 index 00000000000..fba9d9a9ca5 --- /dev/null +++ b/queue-3.18/drm-i915-invalidate-media-caches-on-gen7.patch @@ -0,0 +1,50 @@ +From 148b83d0815a3778c8949e6a97cb798cbaa0efb3 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Tue, 16 Dec 2014 08:44:31 +0000 +Subject: drm/i915: Invalidate media caches on gen7 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit 148b83d0815a3778c8949e6a97cb798cbaa0efb3 upstream. + +In the gen7 pipe control there is an extra bit to flush the media +caches, so let's set it during cache invalidation flushes. + +v2: Rename to MEDIA_STATE_CLEAR to be more inline with spec. + +Cc: Simon Farnsworth +Cc: Ville Syrjälä +Cc: Daniel Vetter +Signed-off-by: Chris Wilson +Reviewed-by: Daniel Vetter +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_reg.h | 1 + + drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + + 2 files changed, 2 insertions(+) + +--- a/drivers/gpu/drm/i915/i915_reg.h ++++ b/drivers/gpu/drm/i915/i915_reg.h +@@ -371,6 +371,7 @@ + #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) + #define PIPE_CONTROL_CS_STALL (1<<20) + #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) ++#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) + #define PIPE_CONTROL_QW_WRITE (1<<14) + #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) + #define PIPE_CONTROL_DEPTH_STALL (1<<13) +--- a/drivers/gpu/drm/i915/intel_ringbuffer.c ++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c +@@ -362,6 +362,7 @@ gen7_render_ring_flush(struct intel_engi + flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; ++ flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; + /* + * TLB invalidate requires a post-sync write. + */ diff --git a/queue-3.18/drm-irq-bug_on-warn_on.patch b/queue-3.18/drm-irq-bug_on-warn_on.patch new file mode 100644 index 00000000000..569f884cc5a --- /dev/null +++ b/queue-3.18/drm-irq-bug_on-warn_on.patch @@ -0,0 +1,37 @@ +From 7f907bf284ba7bb8d271f094b226699d3fef2142 Mon Sep 17 00:00:00 2001 +From: Rob Clark +Date: Sat, 8 Nov 2014 10:16:19 -0500 +Subject: drm/irq: BUG_ON() -> WARN_ON() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Rob Clark + +commit 7f907bf284ba7bb8d271f094b226699d3fef2142 upstream. + +Let's make things a bit easier to debug when things go bad (potentially +under console_lock). + +Signed-off-by: Rob Clark +Reviewed-by: Michel Dänzer +Signed-off-by: Dave Airlie +Cc: Anand Moon +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_irq.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/drm_irq.c ++++ b/drivers/gpu/drm/drm_irq.c +@@ -1029,7 +1029,8 @@ void drm_vblank_put(struct drm_device *d + { + struct drm_vblank_crtc *vblank = &dev->vblank[crtc]; + +- BUG_ON(atomic_read(&vblank->refcount) == 0); ++ if (WARN_ON(atomic_read(&vblank->refcount) == 0)) ++ return; + + if (WARN_ON(crtc >= dev->num_crtcs)) + return; diff --git a/queue-3.18/drm-nv4c-mc-disable-msi.patch b/queue-3.18/drm-nv4c-mc-disable-msi.patch new file mode 100644 index 00000000000..03be22c11c4 --- /dev/null +++ b/queue-3.18/drm-nv4c-mc-disable-msi.patch @@ -0,0 +1,46 @@ +From 4761703bd04bbdf56396d264903cc5a1fdcb3c01 Mon Sep 17 00:00:00 2001 +From: Ilia Mirkin +Date: Tue, 16 Dec 2014 13:55:38 -0500 +Subject: drm/nv4c/mc: disable msi + +From: Ilia Mirkin + +commit 4761703bd04bbdf56396d264903cc5a1fdcb3c01 upstream. + +Several users have, over time, reported issues with MSI on these IGPs. +They're old, rarely available, and MSI doesn't provide such huge +advantages on them. Just disable. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87361 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74492 +Fixes: fa8c9ac72fe ("drm/nv4c/mc: nv4x igp's have a different msi rearm register") +Signed-off-by: Ilia Mirkin +Signed-off-by: Ben Skeggs +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c | 8 -------- + 1 file changed, 8 deletions(-) + +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c ++++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c +@@ -24,13 +24,6 @@ + + #include "nv04.h" + +-static void +-nv4c_mc_msi_rearm(struct nouveau_mc *pmc) +-{ +- struct nv04_mc_priv *priv = (void *)pmc; +- nv_wr08(priv, 0x088050, 0xff); +-} +- + struct nouveau_oclass * + nv4c_mc_oclass = &(struct nouveau_mc_oclass) { + .base.handle = NV_SUBDEV(MC, 0x4c), +@@ -41,5 +34,4 @@ nv4c_mc_oclass = &(struct nouveau_mc_ocl + .fini = _nouveau_mc_fini, + }, + .intr = nv04_mc_intr, +- .msi_rearm = nv4c_mc_msi_rearm, + }.base; diff --git a/queue-3.18/series b/queue-3.18/series index 959bd161437..959b6fa5761 100644 --- a/queue-3.18/series +++ b/queue-3.18/series @@ -42,3 +42,13 @@ drm-i915-disallow-pin-ioctl-completely-for-kms-drivers.patch drm-i915-only-warn-the-first-time-we-attempt-to-mmio-whilst-suspended.patch drm-i915-resume-mst-after-reading-back-hw-state.patch drm-i915-save-restore-gmbus-freq-across-suspend-resume-on-gen4.patch +drm-nv4c-mc-disable-msi.patch +drm-i915-invalidate-media-caches-on-gen7.patch +drm-i915-force-the-cs-stall-for-invalidate-flushes.patch +drm-i915-disable-psmi-sleep-messages-on-all-rings-around-context-switches.patch +drm-i915-don-t-call-intel_prepare_page_flip-multiple-times-on-gen2-4.patch +drm-irq-bug_on-warn_on.patch +arc-move-peripherals-to-match-model-to-fpga.patch +cxl-change-contexts_lock-to-a-mutex-to-fix-sleep-while-atomic-bug.patch +cxl-add-timeout-to-process-element-commands.patch +cxl-unmap-mmio-regions-when-detaching-a-context.patch