From: Yao Zi Date: Fri, 6 Jun 2025 04:28:01 +0000 (+0000) Subject: riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init X-Git-Tag: v2025.10-rc1~134^2~1^2~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5afad3d4a314464af34f9c312d3028b9053f1135;p=thirdparty%2Fu-boot.git riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init C910 cores integrated in TH1520 SoC provide various customized CSRs for configuring core behavior, including cache coherency and timing, branch predication, and clock gating for internal components. This patch sets them up for efficient operation and satisfying requirements of an SMP system. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c index 362fe895f86..b95470485f6 100644 --- a/arch/riscv/cpu/th1520/spl.c +++ b/arch/riscv/cpu/th1520/spl.c @@ -4,6 +4,7 @@ */ #include #include +#include #include #include #include @@ -21,6 +22,52 @@ DECLARE_GLOBAL_DATA_PTR; #define TH1520_SUBSYS_RST_VI_N BIT(1) #define TH1520_SUBSYS_RST_DSP_N BIT(0) +#define CSR_MXSTATUS 0x7c0 +#define CSR_MXSTATUS_THEADISAEE BIT(22) +#define CSR_MXSTATUS_MAEE BIT(21) +#define CSR_MXSTATUS_CLINTEE BIT(17) +#define CSR_MXSTATUS_UCME BIT(16) +#define CSR_MXSTATUS_MM BIT(15) +#define CSR_MHCR 0x7c1 +#define CSR_MHCR_WBR BIT(8) +#define CSR_MHCR_BTB BIT(6) +#define CSR_MHCR_BPE BIT(5) +#define CSR_MHCR_RS BIT(4) +#define CSR_MHCR_WB BIT(3) +#define CSR_MHCR_WA BIT(2) +#define CSR_MHCR_DE BIT(1) +#define CSR_MHCR_IE BIT(0) +#define CSR_MCOR 0x7c2 +#define CSR_MCOR_IBP_INV BIT(18) +#define CSR_MCOR_BTB_INV BIT(17) +#define CSR_MCOR_BHT_INV BIT(16) +#define CSR_MCOR_CACHE_INV BIT(4) +#define CSR_MCCR2 0x7c3 +#define CSR_MCCR2_TPRF BIT(31) +#define CSR_MCCR2_IPRF(n) ((n) << 29) +#define CSR_MCCR2_TSETUP BIT(25) +#define CSR_MCCR2_TLNTCY(n) ((n) << 22) +#define CSR_MCCR2_DSETUP BIT(19) +#define CSR_MCCR2_DLNTCY(n) ((n) << 16) +#define CSR_MCCR2_L2EN BIT(3) +#define CSR_MCCR2_RFE BIT(0) +#define CSR_MHINT 0x7c5 +#define CSR_MHINT_FENCERW_BROAD_DIS BIT(22) +#define CSR_MHINT_TLB_BRAOD_DIS BIT(21) +#define CSR_MHINT_NSFE BIT(18) +#define CSR_MHINT_L2_PREF_DIST(n) ((n) << 16) +#define CSR_MHINT_L2PLD BIT(15) +#define CSR_MHINT_DCACHE_PREF_DIST(n) ((n) << 13) +#define CSR_MHINT_LPE BIT(9) +#define CSR_MHINT_ICACHE_PREF BIT(8) +#define CSR_MHINT_AMR BIT(3) +#define CSR_MHINT_DCACHE_PREF BIT(2) +#define CSR_MHINT2 0x7cc +#define CSR_MHINT2_LOCAL_ICG_EN(n) BIT((n) + 14) +#define CSR_MHINT4 0x7ce +#define CSR_MSMPR 0x7f3 +#define CSR_MSMPR_SMPEN BIT(0) + int spl_dram_init(void) { int ret; @@ -77,6 +124,42 @@ void harts_early_init(void) { int i; + /* Invalidate cache and buffer entries */ + csr_write(CSR_MCOR, CSR_MCOR_IBP_INV | CSR_MCOR_BTB_INV | + CSR_MCOR_BHT_INV | CSR_MCOR_CACHE_INV | 0x3); + + /* Enable cache snooping */ + csr_write(CSR_MSMPR, CSR_MSMPR_SMPEN); + + /* + * Configure and enable L2 cache, + * Enable tag/data RAM prefetch, both cost 2 cycles + * Prefetch 3 cache lines of instructions + * Enable read allocation + */ + csr_write(CSR_MCCR2, CSR_MCCR2_TPRF | CSR_MCCR2_IPRF(3) | + CSR_MCCR2_TSETUP | CSR_MCCR2_TLNTCY(1) | + CSR_MCCR2_DSETUP | CSR_MCCR2_DLNTCY(1) | + CSR_MCCR2_L2EN | CSR_MCCR2_RFE); + csr_write(CSR_MXSTATUS, CSR_MXSTATUS_THEADISAEE | CSR_MXSTATUS_MAEE | + CSR_MXSTATUS_CLINTEE | CSR_MXSTATUS_UCME | + CSR_MXSTATUS_MM); + csr_write(CSR_MHINT, CSR_MHINT_FENCERW_BROAD_DIS | + CSR_MHINT_TLB_BRAOD_DIS | + CSR_MHINT_NSFE | + CSR_MHINT_L2_PREF_DIST(2) | + CSR_MHINT_L2PLD | + CSR_MHINT_DCACHE_PREF_DIST(3) | + CSR_MHINT_LPE | + CSR_MHINT_ICACHE_PREF | + CSR_MHINT_AMR | + CSR_MHINT_DCACHE_PREF); + csr_write(CSR_MHCR, CSR_MHCR_WBR | CSR_MHCR_BTB | CSR_MHCR_BPE | + CSR_MHCR_RS | CSR_MHCR_WB | CSR_MHCR_WA | 0x3); + csr_write(CSR_MHINT2, CSR_MHINT2_LOCAL_ICG_EN(8) | + CSR_MHINT2_LOCAL_ICG_EN(3)); + csr_write(CSR_MHINT4, 0x410); + /* * Set IOPMPs to the default attribute, allowing the application * processor to access various peripherals. Subsystem clocks should be