From: Ingo Molnar <mingo@kernel.org>
Date: Mon, 28 Jul 2025 05:12:53 +0000 (+0200)
Subject: Merge tag 'v6.16' into x86/cpu, to resolve conflict
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5bf2f5119b9e957f773a22f226974166b58cff32;p=thirdparty%2Fkernel%2Flinux.git

Merge tag 'v6.16' into x86/cpu, to resolve conflict

Resolve overlapping context conflict between this upstream fix:

  d8010d4ba43e ("x86/bugs: Add a Transient Scheduler Attacks mitigation")

And this pending commit in tip:x86/cpu:

  65f55a301766 ("x86/CPU/AMD: Add CPUID faulting support")

  Conflicts:
	arch/x86/kernel/cpu/amd.c

Signed-off-by: Ingo Molnar <mingo@kernel.org>
---

5bf2f5119b9e957f773a22f226974166b58cff32
diff --cc arch/x86/include/asm/cpufeatures.h
index b78af55aa22e2,286d509f9363b..602957dd2609c
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -456,8 -456,8 +456,9 @@@
  #define X86_FEATURE_NO_NESTED_DATA_BP	(20*32+ 0) /* No Nested Data Breakpoints */
  #define X86_FEATURE_WRMSR_XX_BASE_NS	(20*32+ 1) /* WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing */
  #define X86_FEATURE_LFENCE_RDTSC	(20*32+ 2) /* LFENCE always serializing / synchronizes RDTSC */
+ #define X86_FEATURE_VERW_CLEAR		(20*32+ 5) /* The memory form of VERW mitigates TSA */
  #define X86_FEATURE_NULL_SEL_CLR_BASE	(20*32+ 6) /* Null Selector Clears Base */
 +
  #define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */
  #define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */
  
diff --cc arch/x86/kernel/cpu/amd.c
index 50f88fe518165,329ee185d8cca..a5ece6ebe8a74
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@@ -489,10 -530,9 +530,11 @@@ static void bsp_init_amd(struct cpuinfo
  	}
  
  	bsp_determine_snp(c);
 -
+ 	tsa_init(c);
  
 +	if (cpu_has(c, X86_FEATURE_GP_ON_USER_CPUID))
 +		setup_force_cpu_cap(X86_FEATURE_CPUID_FAULT);
 +
  	return;
  
  warn: