From: Greg Kroah-Hartman Date: Mon, 15 Apr 2024 13:39:50 +0000 (+0200) Subject: 6.8-stable patches X-Git-Tag: v5.15.156~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5d147c9704f79b61a86a9746c61ea09b76e0d61d;p=thirdparty%2Fkernel%2Fstable-queue.git 6.8-stable patches added patches: drm-amd-display-always-reset-odm-mode-in-context-when-adding-first-plane.patch drm-amd-display-do-not-recursively-call-manual-trigger-programming.patch drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch drm-amd-display-program-vsc-sdp-colorimetry-for-all-dp-sinks-1.4.patch drm-amd-display-return-max-resolution-supported-by-dwb.patch drm-amd-display-set-vsc-sdp-colorimetry-same-way-for-mst-and-sst.patch drm-amdgpu-always-force-full-reset-for-soc21.patch drm-amdgpu-differentiate-external-rev-id-for-gfx-11.5.0.patch drm-amdgpu-fix-incorrect-number-of-active-rbs-for-gfx11.patch drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch drm-i915-disable-live-m-n-updates-when-using-bigjoiner.patch drm-i915-disable-port-sync-when-bigjoiner-is-used.patch drm-i915-psr-disable-psr-when-bigjoiner-is-used.patch --- diff --git a/queue-6.8/drm-amd-display-always-reset-odm-mode-in-context-when-adding-first-plane.patch b/queue-6.8/drm-amd-display-always-reset-odm-mode-in-context-when-adding-first-plane.patch new file mode 100644 index 00000000000..7bbaf022cab --- /dev/null +++ b/queue-6.8/drm-amd-display-always-reset-odm-mode-in-context-when-adding-first-plane.patch @@ -0,0 +1,46 @@ +From 81901d8d0472e9a19d294ae1dea76b950548195d Mon Sep 17 00:00:00 2001 +From: Wenjing Liu +Date: Fri, 22 Mar 2024 15:02:45 -0400 +Subject: drm/amd/display: always reset ODM mode in context when adding first plane + +From: Wenjing Liu + +commit 81901d8d0472e9a19d294ae1dea76b950548195d upstream. + +[why] +In current implemenation ODM mode is only reset when the last plane is +removed from dc state. For any dc validate we will always remove all +current planes and add new planes. However when switching from no planes +to 1 plane, ODM mode is not reset because no planes get removed. This +has caused an issue where we kept ODM combine when it should have been +remove when a plane is added. The change is to reset ODM mode when +adding the first plane. + +Cc: stable@vger.kernel.org +Reviewed-by: Alvin Lee +Acked-by: Hamza Mahfooz +Signed-off-by: Wenjing Liu +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/core/dc_state.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c +@@ -436,6 +436,15 @@ bool dc_state_add_plane( + goto out; + } + ++ if (stream_status->plane_count == 0 && dc->config.enable_windowed_mpo_odm) ++ /* ODM combine could prevent us from supporting more planes ++ * we will reset ODM slice count back to 1 when all planes have ++ * been removed to maximize the amount of planes supported when ++ * new planes are added. ++ */ ++ resource_update_pipes_for_stream_with_slice_count( ++ state, dc->current_state, dc->res_pool, stream, 1); ++ + otg_master_pipe = resource_get_otg_master_for_stream( + &state->res_ctx, stream); + if (otg_master_pipe) diff --git a/queue-6.8/drm-amd-display-do-not-recursively-call-manual-trigger-programming.patch b/queue-6.8/drm-amd-display-do-not-recursively-call-manual-trigger-programming.patch new file mode 100644 index 00000000000..af3ad997277 --- /dev/null +++ b/queue-6.8/drm-amd-display-do-not-recursively-call-manual-trigger-programming.patch @@ -0,0 +1,35 @@ +From 953927587f37b731abdeabe46ad44a3b3ec67a52 Mon Sep 17 00:00:00 2001 +From: Dillon Varone +Date: Thu, 21 Mar 2024 13:49:43 -0400 +Subject: drm/amd/display: Do not recursively call manual trigger programming + +From: Dillon Varone + +commit 953927587f37b731abdeabe46ad44a3b3ec67a52 upstream. + +[WHY&HOW] +We should not be recursively calling the manual trigger programming function when +FAMS is not in use. + +Cc: stable@vger.kernel.org +Reviewed-by: Alvin Lee +Acked-by: Hamza Mahfooz +Signed-off-by: Dillon Varone +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 3 --- + 1 file changed, 3 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c ++++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +@@ -267,9 +267,6 @@ static void optc32_setup_manual_trigger( + OTG_V_TOTAL_MAX_SEL, 1, + OTG_FORCE_LOCK_ON_EVENT, 0, + OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ +- +- // Setup manual flow control for EOF via TRIG_A +- optc->funcs->setup_manual_trigger(optc); + } + } + diff --git a/queue-6.8/drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch b/queue-6.8/drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch new file mode 100644 index 00000000000..2c85a357b97 --- /dev/null +++ b/queue-6.8/drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch @@ -0,0 +1,72 @@ +From cf79814cb0bf5749b9f0db53ca231aa540c02768 Mon Sep 17 00:00:00 2001 +From: Fudongwang +Date: Tue, 26 Mar 2024 16:03:16 +0800 +Subject: drm/amd/display: fix disable otg wa logic in DCN316 + +From: Fudongwang + +commit cf79814cb0bf5749b9f0db53ca231aa540c02768 upstream. + +[Why] +Wrong logic cause screen corruption. + +[How] +Port logic from DCN35/314. + +Cc: stable@vger.kernel.org +Reviewed-by: Nicholas Kazlauskas +Acked-by: Hamza Mahfooz +Signed-off-by: Fudongwang +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c | 19 ++++++---- + 1 file changed, 12 insertions(+), 7 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c +@@ -99,20 +99,25 @@ static int dcn316_get_active_display_cnt + return display_count; + } + +-static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) ++static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, ++ bool safe_to_lower, bool disable) + { + struct dc *dc = clk_mgr_base->ctx->dc; + int i; + + for (i = 0; i < dc->res_pool->pipe_count; ++i) { +- struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; ++ struct pipe_ctx *pipe = safe_to_lower ++ ? &context->res_ctx.pipe_ctx[i] ++ : &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe->top_pipe || pipe->prev_odm_pipe) + continue; +- if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL || +- dc_is_virtual_signal(pipe->stream->signal))) { ++ if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || ++ !pipe->stream->link_enc)) { + if (disable) { +- pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); ++ if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) ++ pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); ++ + reset_sync_context_for_pipe(dc, context, i); + } else + pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); +@@ -207,11 +212,11 @@ static void dcn316_update_clocks(struct + } + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { +- dcn316_disable_otg_wa(clk_mgr_base, context, true); ++ dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); + + clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; + dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); +- dcn316_disable_otg_wa(clk_mgr_base, context, false); ++ dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); + + update_dispclk = true; + } diff --git a/queue-6.8/drm-amd-display-program-vsc-sdp-colorimetry-for-all-dp-sinks-1.4.patch b/queue-6.8/drm-amd-display-program-vsc-sdp-colorimetry-for-all-dp-sinks-1.4.patch new file mode 100644 index 00000000000..4b062892aaf --- /dev/null +++ b/queue-6.8/drm-amd-display-program-vsc-sdp-colorimetry-for-all-dp-sinks-1.4.patch @@ -0,0 +1,51 @@ +From 9e61ef8d219877202d4ee51d0d2ad9072c99a262 Mon Sep 17 00:00:00 2001 +From: Harry Wentland +Date: Tue, 12 Mar 2024 11:55:52 -0400 +Subject: drm/amd/display: Program VSC SDP colorimetry for all DP sinks >= 1.4 + +From: Harry Wentland + +commit 9e61ef8d219877202d4ee51d0d2ad9072c99a262 upstream. + +In order for display colorimetry to work correctly on DP displays +we need to send the VSC SDP packet. We should only do so for +panels with DPCD revision greater or equal to 1.4 as older +receivers might have problems with it. + +Cc: stable@vger.kernel.org +Cc: Joshua Ashton +Cc: Xaver Hugl +Cc: Melissa Wen +Cc: Agustin Gutierrez +Reviewed-by: Agustin Gutierrez +Acked-by: Hamza Mahfooz +Signed-off-by: Harry Wentland +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -6257,7 +6257,9 @@ create_stream_for_sink(struct drm_connec + if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) + mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket); + +- if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) { ++ if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || ++ stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || ++ stream->signal == SIGNAL_TYPE_EDP) { + // + // should decide stream support vsc sdp colorimetry capability + // before building vsc info packet +@@ -6267,7 +6269,8 @@ create_stream_for_sink(struct drm_connec + stream->use_vsc_sdp_for_colorimetry = + aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; + } else { +- if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) ++ if (stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && ++ stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) + stream->use_vsc_sdp_for_colorimetry = true; + } + if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) diff --git a/queue-6.8/drm-amd-display-return-max-resolution-supported-by-dwb.patch b/queue-6.8/drm-amd-display-return-max-resolution-supported-by-dwb.patch new file mode 100644 index 00000000000..01a21360876 --- /dev/null +++ b/queue-6.8/drm-amd-display-return-max-resolution-supported-by-dwb.patch @@ -0,0 +1,37 @@ +From 2cc69a10d83180f3de9f5afe3a98e972b1453d4c Mon Sep 17 00:00:00 2001 +From: Alex Hung +Date: Sat, 23 Mar 2024 12:02:54 -0600 +Subject: drm/amd/display: Return max resolution supported by DWB + +From: Alex Hung + +commit 2cc69a10d83180f3de9f5afe3a98e972b1453d4c upstream. + +mode_config's max width x height is 4096x2160 and is higher than DWB's +max resolution 3840x2160 which is returned instead. + +Cc: stable@vger.kernel.org +Reviewed-by: Harry Wentland +Acked-by: Hamza Mahfooz +Signed-off-by: Alex Hung +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +@@ -76,10 +76,8 @@ static int amdgpu_dm_wb_encoder_atomic_c + + static int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector) + { +- struct drm_device *dev = connector->dev; +- +- return drm_add_modes_noedid(connector, dev->mode_config.max_width, +- dev->mode_config.max_height); ++ /* Maximum resolution supported by DWB */ ++ return drm_add_modes_noedid(connector, 3840, 2160); + } + + static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector, diff --git a/queue-6.8/drm-amd-display-set-vsc-sdp-colorimetry-same-way-for-mst-and-sst.patch b/queue-6.8/drm-amd-display-set-vsc-sdp-colorimetry-same-way-for-mst-and-sst.patch new file mode 100644 index 00000000000..1b8cc67162e --- /dev/null +++ b/queue-6.8/drm-amd-display-set-vsc-sdp-colorimetry-same-way-for-mst-and-sst.patch @@ -0,0 +1,44 @@ +From c3e2a5f2da904a18661335e8be2b961738574998 Mon Sep 17 00:00:00 2001 +From: Harry Wentland +Date: Thu, 21 Mar 2024 11:13:38 -0400 +Subject: drm/amd/display: Set VSC SDP Colorimetry same way for MST and SST + +From: Harry Wentland + +commit c3e2a5f2da904a18661335e8be2b961738574998 upstream. + +The previous check for the is_vsc_sdp_colorimetry_supported flag +for MST sink signals did nothing. Simplify the code and use the +same check for MST and SST. + +Cc: stable@vger.kernel.org +Reviewed-by: Agustin Gutierrez +Acked-by: Hamza Mahfooz +Signed-off-by: Harry Wentland +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++--------- + 1 file changed, 3 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -6264,15 +6264,9 @@ create_stream_for_sink(struct drm_connec + // should decide stream support vsc sdp colorimetry capability + // before building vsc info packet + // +- stream->use_vsc_sdp_for_colorimetry = false; +- if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { +- stream->use_vsc_sdp_for_colorimetry = +- aconnector->dc_sink->is_vsc_sdp_colorimetry_supported; +- } else { +- if (stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && +- stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED) +- stream->use_vsc_sdp_for_colorimetry = true; +- } ++ stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && ++ stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED; ++ + if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) + tf = TRANSFER_FUNC_GAMMA_22; + mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf); diff --git a/queue-6.8/drm-amdgpu-always-force-full-reset-for-soc21.patch b/queue-6.8/drm-amdgpu-always-force-full-reset-for-soc21.patch new file mode 100644 index 00000000000..08c865f8b2d --- /dev/null +++ b/queue-6.8/drm-amdgpu-always-force-full-reset-for-soc21.patch @@ -0,0 +1,33 @@ +From 65ff8092e4802f96d87d3d7cde146961f5228265 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Sat, 23 Mar 2024 20:46:53 -0400 +Subject: drm/amdgpu: always force full reset for SOC21 + +From: Alex Deucher + +commit 65ff8092e4802f96d87d3d7cde146961f5228265 upstream. + +There are cases where soft reset seems to succeed, but +does not, so always use mode1/2 for now. + +Reviewed-by: Harish Kasiviswanathan +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 2 -- + 1 file changed, 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -450,10 +450,8 @@ static bool soc21_need_full_reset(struct + { + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(11, 0, 0): +- return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC); + case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): +- return false; + default: + return true; + } diff --git a/queue-6.8/drm-amdgpu-differentiate-external-rev-id-for-gfx-11.5.0.patch b/queue-6.8/drm-amdgpu-differentiate-external-rev-id-for-gfx-11.5.0.patch new file mode 100644 index 00000000000..50e6938f03f --- /dev/null +++ b/queue-6.8/drm-amdgpu-differentiate-external-rev-id-for-gfx-11.5.0.patch @@ -0,0 +1,34 @@ +From 6dba20d23e85034901ccb765a7ca71199bcca4df Mon Sep 17 00:00:00 2001 +From: Yifan Zhang +Date: Sun, 7 Apr 2024 22:01:35 +0800 +Subject: drm/amdgpu: differentiate external rev id for gfx 11.5.0 + +From: Yifan Zhang + +commit 6dba20d23e85034901ccb765a7ca71199bcca4df upstream. + +This patch to differentiate external rev id for gfx 11.5.0. + +Signed-off-by: Yifan Zhang +Reviewed-by: Tim Huang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -712,7 +712,10 @@ static int soc21_common_early_init(void + AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_JPEG | + AMD_PG_SUPPORT_GFX_PG; +- adev->external_rev_id = adev->rev_id + 0x1; ++ if (adev->rev_id == 0) ++ adev->external_rev_id = 0x1; ++ else ++ adev->external_rev_id = adev->rev_id + 0x10; + break; + default: + /* FIXME: not supported yet */ diff --git a/queue-6.8/drm-amdgpu-fix-incorrect-number-of-active-rbs-for-gfx11.patch b/queue-6.8/drm-amdgpu-fix-incorrect-number-of-active-rbs-for-gfx11.patch new file mode 100644 index 00000000000..2067d30f59a --- /dev/null +++ b/queue-6.8/drm-amdgpu-fix-incorrect-number-of-active-rbs-for-gfx11.patch @@ -0,0 +1,32 @@ +From bbca7f414ae9a12ea231cdbafd79c607e3337ea8 Mon Sep 17 00:00:00 2001 +From: Tim Huang +Date: Wed, 3 Apr 2024 17:28:44 +0800 +Subject: drm/amdgpu: fix incorrect number of active RBs for gfx11 + +From: Tim Huang + +commit bbca7f414ae9a12ea231cdbafd79c607e3337ea8 upstream. + +The RB bitmap should be global active RB bitmap & +active RB bitmap based on active SA. + +Signed-off-by: Tim Huang +Reviewed-by: Yifan Zhang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -1630,7 +1630,7 @@ static void gfx_v11_0_setup_rb(struct am + active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); + } + +- active_rb_bitmap |= global_active_rb_bitmap; ++ active_rb_bitmap &= global_active_rb_bitmap; + adev->gfx.config.backend_enable_mask = active_rb_bitmap; + adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); + } diff --git a/queue-6.8/drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch b/queue-6.8/drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch new file mode 100644 index 00000000000..7f854e5ef41 --- /dev/null +++ b/queue-6.8/drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch @@ -0,0 +1,62 @@ +From 8b2be55f4d6c1099d7f629b0ed7535a5be788c83 Mon Sep 17 00:00:00 2001 +From: Lijo Lazar +Date: Wed, 14 Feb 2024 17:55:54 +0530 +Subject: drm/amdgpu: Reset dGPU if suspend got aborted + +From: Lijo Lazar + +commit 8b2be55f4d6c1099d7f629b0ed7535a5be788c83 upstream. + +For SOC21 ASICs, there is an issue in re-enabling PM features if a +suspend got aborted. In such cases, reset the device during resume +phase. This is a workaround till a proper solution is finalized. + +Signed-off-by: Lijo Lazar +Reviewed-by: Alex Deucher +Reviewed-by: Yang Wang +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/soc21.c | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/soc21.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc21.c +@@ -832,10 +832,35 @@ static int soc21_common_suspend(void *ha + return soc21_common_hw_fini(adev); + } + ++static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) ++{ ++ u32 sol_reg1, sol_reg2; ++ ++ /* Will reset for the following suspend abort cases. ++ * 1) Only reset dGPU side. ++ * 2) S3 suspend got aborted and TOS is active. ++ */ ++ if (!(adev->flags & AMD_IS_APU) && adev->in_s3 && ++ !adev->suspend_complete) { ++ sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); ++ msleep(100); ++ sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); ++ ++ return (sol_reg1 != sol_reg2); ++ } ++ ++ return false; ++} ++ + static int soc21_common_resume(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + ++ if (soc21_need_reset_on_resume(adev)) { ++ dev_info(adev->dev, "S3 suspend aborted, resetting..."); ++ soc21_asic_reset(adev); ++ } ++ + return soc21_common_hw_init(adev); + } + diff --git a/queue-6.8/drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch b/queue-6.8/drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch new file mode 100644 index 00000000000..b7f72c5d971 --- /dev/null +++ b/queue-6.8/drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch @@ -0,0 +1,106 @@ +From 7b1f6b5aaec0f849e19c3e99d4eea75876853cdd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Tue, 2 Apr 2024 18:50:03 +0300 +Subject: drm/i915/cdclk: Fix CDCLK programming order when pipes are active +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 7b1f6b5aaec0f849e19c3e99d4eea75876853cdd upstream. + +Currently we always reprogram CDCLK from the +intel_set_cdclk_pre_plane_update() when using squash/crawl. +The code only works correctly for the cd2x update or full +modeset cases, and it was simply never updated to deal with +squash/crawl. + +If the CDCLK frequency is increasing we must reprogram it +before we do anything else that might depend on the new +higher frequency, and conversely we must not decrease +the frequency until everything that might still depend +on the old higher frequency has been dealt with. + +Since cdclk_state->pipe is only relevant when doing a cd2x +update we can't use it to determine the correct sequence +during squash/crawl. To that end introduce cdclk_state->disable_pipes +which simply indicates that we must perform the update +while the pipes are disable (ie. during +intel_set_cdclk_pre_plane_update()). Otherwise we use the +same old vs. new CDCLK frequency comparsiong as for cd2x +updates. + +The only remaining problem case is when the voltage_level +needs to increase due to a DDI port, but the CDCLK frequency +is decreasing (and not all pipes are being disabled). The +current approach will not bump the voltage level up until +after the port has already been enabled, which is too late. +But we'll take care of that case separately. + +v2: Don't break the "must disable pipes case" +v3: Keep the on stack 'pipe' for future use + +Cc: stable@vger.kernel.org +Fixes: d62686ba3b54 ("drm/i915/adl_p: CDCLK crawl support for ADL") +Reviewed-by: Uma Shankar +Reviewed-by: Gustavo Sousa +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-2-ville.syrjala@linux.intel.com +(cherry picked from commit 3aecee90ac12a351905f12dda7643d5b0676d6ca) +Signed-off-by: Rodrigo Vivi +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++++-- + drivers/gpu/drm/i915/display/intel_cdclk.h | 3 +++ + 2 files changed, 8 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_cdclk.c ++++ b/drivers/gpu/drm/i915/display/intel_cdclk.c +@@ -2521,7 +2521,7 @@ intel_set_cdclk_pre_plane_update(struct + if (IS_DG2(i915)) + intel_cdclk_pcode_pre_notify(state); + +- if (pipe == INVALID_PIPE || ++ if (new_cdclk_state->disable_pipes || + old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { + drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); + +@@ -2553,7 +2553,7 @@ intel_set_cdclk_post_plane_update(struct + if (IS_DG2(i915)) + intel_cdclk_pcode_post_notify(state); + +- if (pipe != INVALID_PIPE && ++ if (!new_cdclk_state->disable_pipes && + old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { + drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); + +@@ -3036,6 +3036,7 @@ static struct intel_global_state *intel_ + return NULL; + + cdclk_state->pipe = INVALID_PIPE; ++ cdclk_state->disable_pipes = false; + + return &cdclk_state->base; + } +@@ -3214,6 +3215,8 @@ int intel_modeset_calc_cdclk(struct inte + if (ret) + return ret; + ++ new_cdclk_state->disable_pipes = true; ++ + drm_dbg_kms(&dev_priv->drm, + "Modeset required for cdclk change\n"); + } +--- a/drivers/gpu/drm/i915/display/intel_cdclk.h ++++ b/drivers/gpu/drm/i915/display/intel_cdclk.h +@@ -51,6 +51,9 @@ struct intel_cdclk_state { + + /* bitmask of active pipes */ + u8 active_pipes; ++ ++ /* update cdclk with pipes disabled */ ++ bool disable_pipes; + }; + + int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); diff --git a/queue-6.8/drm-i915-disable-live-m-n-updates-when-using-bigjoiner.patch b/queue-6.8/drm-i915-disable-live-m-n-updates-when-using-bigjoiner.patch new file mode 100644 index 00000000000..67560d72a84 --- /dev/null +++ b/queue-6.8/drm-i915-disable-live-m-n-updates-when-using-bigjoiner.patch @@ -0,0 +1,44 @@ +From 4a36e46df7aa781c756f09727d37dc2783f1ee75 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Fri, 5 Apr 2024 00:34:28 +0300 +Subject: drm/i915: Disable live M/N updates when using bigjoiner +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 4a36e46df7aa781c756f09727d37dc2783f1ee75 upstream. + +All joined pipes share the same transcoder/timing generator. +Currently we just do the commits per-pipe, which doesn't really +work if we need to change the timings at the same time. For +now just disable live M/N updates when bigjoiner is needed. + +Cc: stable@vger.kernel.org +Tested-by: Vidya Srinivas +Reviewed-by: Arun R Murthy +Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-5-ville.syrjala@linux.intel.com +Signed-off-by: Ville Syrjälä +(cherry picked from commit ef79820db723a2a7c229a7251c12859e7e25a247) +Signed-off-by: Rodrigo Vivi +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_dp.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/display/intel_dp.c ++++ b/drivers/gpu/drm/i915/display/intel_dp.c +@@ -2756,7 +2756,11 @@ intel_dp_drrs_compute_config(struct inte + intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); + int pixel_clock; + +- if (has_seamless_m_n(connector)) ++ /* ++ * FIXME all joined pipes share the same transcoder. ++ * Need to account for that when updating M/N live. ++ */ ++ if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes) + pipe_config->update_m_n = true; + + if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { diff --git a/queue-6.8/drm-i915-disable-port-sync-when-bigjoiner-is-used.patch b/queue-6.8/drm-i915-disable-port-sync-when-bigjoiner-is-used.patch new file mode 100644 index 00000000000..a78500e5134 --- /dev/null +++ b/queue-6.8/drm-i915-disable-port-sync-when-bigjoiner-is-used.patch @@ -0,0 +1,45 @@ +From 0653d501409eeb9f1deb7e4c12e4d0d2c9f1cba1 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Fri, 5 Apr 2024 00:34:27 +0300 +Subject: drm/i915: Disable port sync when bigjoiner is used +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 0653d501409eeb9f1deb7e4c12e4d0d2c9f1cba1 upstream. + +The current modeset sequence can't handle port sync and bigjoiner +at the same time. Refuse port sync when bigjoiner is needed, +at least until we fix the modeset sequence. + +v2: Add a FIXME (Vandite) + +Cc: stable@vger.kernel.org +Tested-by: Vidya Srinivas +Reviewed-by: Vandita Kulkarni +Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-4-ville.syrjala@linux.intel.com +Signed-off-by: Ville Syrjälä +(cherry picked from commit b37e1347b991459c38c56ec2476087854a4f720b) +Signed-off-by: Rodrigo Vivi +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_ddi.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/gpu/drm/i915/display/intel_ddi.c ++++ b/drivers/gpu/drm/i915/display/intel_ddi.c +@@ -4229,7 +4229,12 @@ static bool m_n_equal(const struct intel + static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, + const struct intel_crtc_state *crtc_state2) + { ++ /* ++ * FIXME the modeset sequence is currently wrong and ++ * can't deal with bigjoiner + port sync at the same time. ++ */ + return crtc_state1->hw.active && crtc_state2->hw.active && ++ !crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes && + crtc_state1->output_types == crtc_state2->output_types && + crtc_state1->output_format == crtc_state2->output_format && + crtc_state1->lane_count == crtc_state2->lane_count && diff --git a/queue-6.8/drm-i915-psr-disable-psr-when-bigjoiner-is-used.patch b/queue-6.8/drm-i915-psr-disable-psr-when-bigjoiner-is-used.patch new file mode 100644 index 00000000000..98512800f1b --- /dev/null +++ b/queue-6.8/drm-i915-psr-disable-psr-when-bigjoiner-is-used.patch @@ -0,0 +1,49 @@ +From e3d4ead4d48c05355bd3b99c8162428f68c3c1a5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Fri, 5 Apr 2024 00:34:26 +0300 +Subject: drm/i915/psr: Disable PSR when bigjoiner is used +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit e3d4ead4d48c05355bd3b99c8162428f68c3c1a5 upstream. + +Bigjoiner seem to be causing all kinds of grief to the PSR +code currently. I don't believe there is any hardware issue +but the code simply not handling this correctly. For now +just disable PSR when bigjoiner is needed. + +Cc: stable@vger.kernel.org +Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-3-ville.syrjala@linux.intel.com +Reviewed-by: Arun R Murthy +Acked-by: Jouni Högander +Signed-off-by: Ville Syrjälä +(cherry picked from commit 372fa0c79d3f289f813d8001e0a8a96d1011826c) +Signed-off-by: Rodrigo Vivi +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_psr.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/drivers/gpu/drm/i915/display/intel_psr.c ++++ b/drivers/gpu/drm/i915/display/intel_psr.c +@@ -1368,6 +1368,17 @@ void intel_psr_compute_config(struct int + return; + } + ++ /* ++ * FIXME figure out what is wrong with PSR+bigjoiner and ++ * fix it. Presumably something related to the fact that ++ * PSR is a transcoder level feature. ++ */ ++ if (crtc_state->bigjoiner_pipes) { ++ drm_dbg_kms(&dev_priv->drm, ++ "PSR disabled due to bigjoiner\n"); ++ return; ++ } ++ + if (CAN_PANEL_REPLAY(intel_dp)) + crtc_state->has_panel_replay = true; + else diff --git a/queue-6.8/series b/queue-6.8/series index b02cb7d3378..e833cc5a259 100644 --- a/queue-6.8/series +++ b/queue-6.8/series @@ -156,3 +156,17 @@ x86-bugs-fix-bhi-handling-of-rrsba.patch x86-bugs-clarify-that-syscall-hardening-isn-t-a-bhi-mitigation.patch x86-bugs-remove-config_bhi_mitigation_auto-and-spectre_bhi-auto.patch x86-bugs-replace-config_spectre_bhi_-on-off-with-config_mitigation_spectre_bhi.patch +drm-i915-cdclk-fix-cdclk-programming-order-when-pipes-are-active.patch +drm-i915-psr-disable-psr-when-bigjoiner-is-used.patch +drm-i915-disable-port-sync-when-bigjoiner-is-used.patch +drm-i915-disable-live-m-n-updates-when-using-bigjoiner.patch +drm-amdgpu-reset-dgpu-if-suspend-got-aborted.patch +drm-amdgpu-always-force-full-reset-for-soc21.patch +drm-amdgpu-fix-incorrect-number-of-active-rbs-for-gfx11.patch +drm-amdgpu-differentiate-external-rev-id-for-gfx-11.5.0.patch +drm-amd-display-program-vsc-sdp-colorimetry-for-all-dp-sinks-1.4.patch +drm-amd-display-set-vsc-sdp-colorimetry-same-way-for-mst-and-sst.patch +drm-amd-display-do-not-recursively-call-manual-trigger-programming.patch +drm-amd-display-return-max-resolution-supported-by-dwb.patch +drm-amd-display-always-reset-odm-mode-in-context-when-adding-first-plane.patch +drm-amd-display-fix-disable-otg-wa-logic-in-dcn316.patch