From: Biju Das Date: Mon, 25 Apr 2022 09:52:44 +0000 (+0100) Subject: clk: renesas: r9a07g043: Add WDT clock and reset entries X-Git-Tag: v5.19-rc1~117^2~3^5^2~26 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5d33481f54758eb050473af0692a043c084ad581;p=thirdparty%2Fkernel%2Flinux.git clk: renesas: r9a07g043: Add WDT clock and reset entries Add WDT{0,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220425095244.156720-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c index d0721bef5c146..3f3c5d1b7fec1 100644 --- a/drivers/clk/renesas/r9a07g043-cpg.c +++ b/drivers/clk/renesas/r9a07g043-cpg.c @@ -135,6 +135,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 0x534, 1), DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 0x534, 2), + DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, + 0x548, 0), + DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, + 0x548, 1), + DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0, + 0x548, 4), + DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK, + 0x548, 5), DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, @@ -220,6 +228,8 @@ static struct rzg2l_reset r9a07g043_resets[] = { DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), + DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), + DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2), DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),