From: Greg Kroah-Hartman Date: Mon, 13 Jul 2026 13:20:34 +0000 (+0200) Subject: 6.12-stable patches X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5d7d3fbc428363ae0929717786814e660f57d733;p=thirdparty%2Fkernel%2Fstable-queue.git 6.12-stable patches added patches: pci-altera-do-not-dispose-parent-irq-mapping.patch pci-loongson-override-pcie-bridge-supported-speeds-for-loongson-3c6000-series.patch --- diff --git a/queue-6.12/pci-altera-do-not-dispose-parent-irq-mapping.patch b/queue-6.12/pci-altera-do-not-dispose-parent-irq-mapping.patch new file mode 100644 index 0000000000..3c104be731 --- /dev/null +++ b/queue-6.12/pci-altera-do-not-dispose-parent-irq-mapping.patch @@ -0,0 +1,46 @@ +From 5ef4bac02189bee0b7c170e352d7a38e13fe9678 Mon Sep 17 00:00:00 2001 +From: Mahesh Vaidya +Date: Thu, 30 Apr 2026 13:43:29 -0700 +Subject: PCI: altera: Do not dispose parent IRQ mapping + +From: Mahesh Vaidya + +commit 5ef4bac02189bee0b7c170e352d7a38e13fe9678 upstream. + +altera_pcie_irq_teardown() calls irq_dispose_mapping() on pcie->irq. +However, pcie->irq is the parent IRQ returned by platform_get_irq(), not +the mapping created by Altera INTx irq_domain. + +The Altera driver only sets the chained handler on the parent IRQ. It +should detach that handler during teardown, but it should not dispose the +parent IRQ mapping, which belongs to the parent interrupt controller's +irq_domain. + +Drop irq_dispose_mapping(pcie->irq) from the teardown path. + +Note that during irqchip remove(), the child IRQs should've disposed. But +since the chained handler itself is removed, there is no way the stale +child IRQs (if exists) could fire. So it is safe here. + +Fixes: ec15c4d0d5d2 ("PCI: altera: Allow building as module") +Signed-off-by: Mahesh Vaidya +[mani: added a note about IRQ disposal] +Signed-off-by: Manivannan Sadhasivam +Reviewed-by: Subhransu S. Prusty +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/20260430204330.3121003-2-mahesh.vaidya@altera.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-altera.c | 1 - + 1 file changed, 1 deletion(-) + +--- a/drivers/pci/controller/pcie-altera.c ++++ b/drivers/pci/controller/pcie-altera.c +@@ -683,7 +683,6 @@ static void altera_pcie_irq_teardown(str + { + irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); + irq_domain_remove(pcie->irq_domain); +- irq_dispose_mapping(pcie->irq); + } + + static int altera_pcie_parse_dt(struct altera_pcie *pcie) diff --git a/queue-6.12/pci-loongson-override-pcie-bridge-supported-speeds-for-loongson-3c6000-series.patch b/queue-6.12/pci-loongson-override-pcie-bridge-supported-speeds-for-loongson-3c6000-series.patch new file mode 100644 index 0000000000..b5df427f8b --- /dev/null +++ b/queue-6.12/pci-loongson-override-pcie-bridge-supported-speeds-for-loongson-3c6000-series.patch @@ -0,0 +1,93 @@ +From e373c789bac0ad73b472d8b44714df3bd18a4edf Mon Sep 17 00:00:00 2001 +From: Ziyao Li +Date: Sun, 12 Apr 2026 18:17:31 +0800 +Subject: PCI: loongson: Override PCIe bridge supported speeds for Loongson-3C6000 series + +From: Ziyao Li + +commit e373c789bac0ad73b472d8b44714df3bd18a4edf upstream. + +Older steppings of the Loongson-3C6000 series incorrectly report the +supported link speeds on their PCIe bridges (device IDs 0x3c19, 0x3c29) +as only 2.5 GT/s, despite the upstream bus supporting speeds from +2.5 GT/s up to 16 GT/s. + +As a result, since commit 774c71c52aa4 ("PCI/bwctrl: Enable only if more +than one speed is supported"), bwctrl will be disabled if there's only +one 2.5 GT/s value in vector 'supported_speeds'. + +Manually override the 'supported_speeds' field for affected PCIe bridges +with those found on the upstream bus to correctly reflect the supported +link speeds. Updating the speeds to reflect what the hardware actually +supports avoids quirks in drivers consuming the speed information. + +This commit was originally found from AOSC OS[1]. + +Fixes: cd89edda4002 ("PCI: loongson: Add ACPI init support") +Signed-off-by: Ayden Meng +Signed-off-by: Mingcong Bai +[Ziyao Li: move from drivers/pci/quirks.c to drivers/pci/controller/pci-loongson.c] +Signed-off-by: Ziyao Li +[Xi Ruoyao: Fixed falling through logic, added debug log, Fixes tag and rebased to 7.0-rc7] +Signed-off-by: Xi Ruoyao +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: commit log, https://lore.kernel.org/all/9d815df3b33a63223112b97440c01247935363c1.camel@xry111.site] +Signed-off-by: Bjorn Helgaas +Tested-by: Lain Fearyncess Yang +Tested-by: Ayden Meng +Tested-by: Mingcong Bai +Reviewed-by: Huacai Chen +Cc: stable@vger.kernel.org +Link: https://github.com/AOSC-Tracking/linux/commit/4392f441363abdf6fa0a0433d73175a17f493454 +Link: https://github.com/AOSC-Tracking/linux/pull/2 #1 +Link: https://patch.msgid.link/20260412101731.107059-1-xry111@xry111.site +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pci-loongson.c | 36 ++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/drivers/pci/controller/pci-loongson.c ++++ b/drivers/pci/controller/pci-loongson.c +@@ -176,6 +176,42 @@ static void loongson_pci_msi_quirk(struc + } + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, DEV_LS7A_PCIE_PORT5, loongson_pci_msi_quirk); + ++/* ++ * Older steppings of the Loongson-3C6000 series incorrectly report the ++ * supported link speeds on their PCIe bridges (device IDs 0x3c19, ++ * 0x3c29) as only 2.5 GT/s, despite the upstream bus supporting speeds ++ * from 2.5 GT/s up to 16 GT/s. ++ */ ++static void loongson_pci_bridge_speed_quirk(struct pci_dev *pdev) ++{ ++ u8 old_supported_speeds = pdev->supported_speeds; ++ ++ switch (pdev->bus->max_bus_speed) { ++ case PCIE_SPEED_16_0GT: ++ pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_16_0GB; ++ fallthrough; ++ case PCIE_SPEED_8_0GT: ++ pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_8_0GB; ++ fallthrough; ++ case PCIE_SPEED_5_0GT: ++ pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_5_0GB; ++ fallthrough; ++ case PCIE_SPEED_2_5GT: ++ pdev->supported_speeds |= PCI_EXP_LNKCAP2_SLS_2_5GB; ++ break; ++ default: ++ pci_warn(pdev, "unexpected max bus speed"); ++ ++ return; ++ } ++ ++ if (pdev->supported_speeds != old_supported_speeds) ++ pci_info(pdev, "fixed up supported link speeds: 0x%x => 0x%x", ++ old_supported_speeds, pdev->supported_speeds); ++} ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c19, loongson_pci_bridge_speed_quirk); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON, 0x3c29, loongson_pci_bridge_speed_quirk); ++ + static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus) + { + struct pci_config_window *cfg; diff --git a/queue-6.12/series b/queue-6.12/series index b5108762ae..e9f31952f0 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -98,3 +98,5 @@ binder-fix-uaf-in-binder_thread_release.patch binder-fix-uaf-in-binder_free_transaction.patch usb-xhci-fix-sleep-in-atomic-context-in-xhci_free_streams.patch usb-typec-tcpci_rt1711h-unregister-tcpci-port-with-devres.patch +pci-loongson-override-pcie-bridge-supported-speeds-for-loongson-3c6000-series.patch +pci-altera-do-not-dispose-parent-irq-mapping.patch