From: Nelson Chu <nelson.chu@sifive.com>
Date: Tue, 21 Apr 2020 06:42:20 +0000 (+0800)
Subject: RISC-V/zfh: Support .float16 directive for assembler.
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5e1f22d21a9b0d7e23e2e5aef5d418f10c39941b;p=thirdparty%2Fbinutils-gdb.git

RISC-V/zfh: Support .float16 directive for assembler.

This probably need to be sent to mainline rather than here.

gas/
    * config/tc-riscv.c (FLT_CHARS): Added h and H.
    (riscv_pseudo_table): Added .float16.
    * read.c (hex_float): Handle case 'h' and 'H'.
    * testsuite/gas/riscv/extended/extended.exp: Updated.
    * testsuite/gas/riscv/extended/float16.d: New testcase.
    * testsuite/gas/riscv/extended/float16.s: Likewise.
---

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 2ec97b83cff..1661397c6ec 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -597,7 +597,7 @@ const char EXP_CHARS[] = "eE";
 
 /* Chars that mean this number is a floating point constant.
    As in 0f12.456 or 0d1.2345e12.  */
-const char FLT_CHARS[] = "rRsSfFdDxXpP";
+const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
 
 /* Indicate we are already assemble any instructions or not.  */
 static bool start_assemble = false;
@@ -4571,6 +4571,7 @@ static const pseudo_typeS riscv_pseudo_table[] =
   {"sleb128", s_riscv_leb128, 1},
   {"insn", s_riscv_insn, 0},
   {"attribute", s_riscv_attribute, 0},
+  {"float16", float_cons, 'h'},
 
   { NULL, NULL, 0 },
 };
diff --git a/gas/read.c b/gas/read.c
index 935b1fa7bde..5c7c7399caa 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -4824,6 +4824,11 @@ hex_float (int float_type, char *bytes)
 
   switch (float_type)
     {
+    case 'h':
+    case 'H':
+      length = 2;
+      break;
+
     case 'f':
     case 'F':
     case 's':
diff --git a/gas/testsuite/gas/riscv/extended/extended.exp b/gas/testsuite/gas/riscv/extended/extended.exp
index 3ad8833ea84..2b36cc548cc 100644
--- a/gas/testsuite/gas/riscv/extended/extended.exp
+++ b/gas/testsuite/gas/riscv/extended/extended.exp
@@ -32,6 +32,7 @@ if [istarget riscv*-*-*] {
     run_dump_tests "vector-insns-fail-permutation"
     run_dump_tests "vector-insns-fail-zvamo"
     run_dump_tests "fp-zfh-insns"
+    run_dump_tests "float16"
 
     run_dump_tests "extended-csr"
 }
diff --git a/gas/testsuite/gas/riscv/extended/float16.d b/gas/testsuite/gas/riscv/extended/float16.d
new file mode 100644
index 00000000000..e75971d9417
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/float16.d
@@ -0,0 +1,10 @@
+# source: float16.s
+# objdump: -sj .data
+# as:
+
+.*:[ 	]+file format .*
+
+Contents of section \.data:
+ 0000 004adf2f 191cff7b 0100ff03 0004003c.*
+ 0010 013cff7f 007c00fc 00000080 00bce7bb.*
+ 0020 fffb0042 004a3e60 007e017e.*
diff --git a/gas/testsuite/gas/riscv/extended/float16.s b/gas/testsuite/gas/riscv/extended/float16.s
new file mode 100644
index 00000000000..709ea0af7ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/float16.s
@@ -0,0 +1,21 @@
+.data
+	.float16 12.0
+	.float16 0.123
+	.float16 0.004
+	.float16 65504
+	.float16 5.9605e-8
+	.float16 6.0976e-5
+	.float16 6.1035e-5
+	.float16 1
+	.float16 1.001
+	.float16 NaN
+	.float16 +Inf
+	.float16 -Inf
+	.float16 +0
+	.float16 -0
+	.float16 -1
+	.float16 -0.98765
+	.float16 -65504
+	.float16 3.0, 12.0, 543.123
+	.float16 0h:7e00	# qNaNh
+	.float16 0h:7e01	# sNaNh