From: Frank Chang <frank.chang@sifive.com>
Date: Tue, 23 Feb 2021 06:59:32 +0000 (+0800)
Subject: target/riscv: fix vs() to return proper error code
X-Git-Tag: v6.0.0-rc0~7^2~15
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5e437d3ccdccfd85f6e69ca60f921be2dab62c3c;p=thirdparty%2Fqemu.git

target/riscv: fix vs() to return proper error code

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fd2e6363f39..d2ae73e4a08 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -54,7 +54,7 @@ static int vs(CPURISCVState *env, int csrno)
     if (env->misa & RVV) {
         return 0;
     }
-    return -1;
+    return -RISCV_EXCP_ILLEGAL_INST;
 }
 
 static int ctr(CPURISCVState *env, int csrno)