From: Stafford Horne Date: Sun, 1 Jun 2025 05:39:01 +0000 (+0100) Subject: or1k: Add support for numcores and coreid sprs X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5eb0dd3623c49c9bd439b9435c35fe99ac026d39;p=thirdparty%2Fbinutils-gdb.git or1k: Add support for numcores and coreid sprs These are needed when running GCC tests for newlib toolchains built with multicore support. Without these SPRs we get the following warnings when running tests. spawn or1k-elf-run ./20000112-1.exe^M WARNING: l.mfspr with invalid SPR address 0x80^M WARNING: l.mfspr with invalid SPR address 0x81^M WARNING: l.mfspr with invalid SPR address 0x81^M WARNING: l.mfspr with invalid SPR address 0x81^M Support is added by defining the SPRs in the cgen machine definition and regenerating the machine code. In or1k/or1k.c we initialize NUMCORES to 1 and COREID to 0 as the sim has only one CPU. In or1k/traps.c we allow returning the NUMCORES and COREID spr values in the mfspr function. Signed-off-by: Stafford Horne --- diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu index 9f102c93a18..7f91954e570 100644 --- a/cpu/or1kcommon.cpu +++ b/cpu/or1kcommon.cpu @@ -243,6 +243,8 @@ (.unsplice (.map (.pmacro (n) (.splice SYS (.sym "ESR" n) (.add n #x40) (.str "Exception supervision register " n))) (.iota #x10))) + (SYS COREID #x080 "Core identifier register") + (SYS NUMCORES #x081 "Number of cores register") (.unsplice (.map (.pmacro (n) (.splice SYS (.sym "GPR" n) (.add n #x400) (.str "General purpose register " n))) (.iota #x200))) diff --git a/opcodes/or1k-desc.c b/opcodes/or1k-desc.c index 9b8aa08699f..90db200fc6c 100644 --- a/opcodes/or1k-desc.c +++ b/opcodes/or1k-desc.c @@ -302,6 +302,8 @@ const CGEN_HW_ENTRY or1k_cgen_hw_table[] = { "h-sys-esr13", HW_H_SYS_ESR13, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<