From: Marc Zyngier <marc.zyngier@arm.com>
Date: Sat, 1 Jul 2017 14:16:35 +0000 (+0100)
Subject: ARM64: dts: marvell: armada-37xx: Enable memory-mapped GIC CPU interface
X-Git-Tag: v4.14-rc1~66^2^2~23^2~9
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5f926e889fcdb4aab32caf7ebe1c42dd7c2a4e64;p=thirdparty%2Fkernel%2Flinux.git

ARM64: dts: marvell: armada-37xx: Enable memory-mapped GIC CPU interface

The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a GIC CPU interface that gets enabled when coupled with a GICv3
interrupt controller, such as the GIC-500 on the this SoC.

Advertise the MMIO ranges provided by the CPUs, which enables
(among other things) GICv2 guests to run under a hypervisor such
as KVM.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---

diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index a92ac63addf07..b6f1e7a5e5ec0 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -322,7 +322,10 @@
 				#interrupt-cells = <3>;
 				interrupt-controller;
 				reg = <0x1d00000 0x10000>, /* GICD */
-				      <0x1d40000 0x40000>; /* GICR */
+				      <0x1d40000 0x40000>, /* GICR */
+				      <0x1d80000 0x2000>,  /* GICC */
+				      <0x1d90000 0x2000>,  /* GICH */
+				      <0x1da0000 0x20000>; /* GICV */
 				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			};
 		};