From: Kewen Lin <linkw@linux.ibm.com>
Date: Thu, 21 Dec 2023 05:20:19 +0000 (-0600)
Subject: sel-sched: Verify change before replacing dest in EXPR_INSN_RTX [PR112995]
X-Git-Tag: basepoints/gcc-15~3371
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=5fbc77726f68a35a938c829fe259d6c376d608ca;p=thirdparty%2Fgcc.git

sel-sched: Verify change before replacing dest in EXPR_INSN_RTX [PR112995]

PR112995 exposed one issue in current try_replace_dest_reg
that the result rtx insn after replace_dest_with_reg_in_expr
is probably unable to match any constraints.  Although there
are some checks on the changes onto dest or src of orig_insn,
none is performed on the EXPR_INSN_RTX.

Initially we have:

(insn 31 6 10 2 (set (reg/v:SI 9 9 [orig:119 c ] [119])
                     (reg/v:SI 64 0 [orig:119 c ] [119]))
                "test.i":5:5 555 {*movsi_internal1} ... )
...
(insn 25 10 27 2 (set (reg:DI 64 0 [135])
                      (sign_extend:DI
                         (reg/v:SI 9 9 [orig:119 c ] [119])))
                 "test.i":6:5 31 {extendsidi2} ...)

with moving up, we have:

(insn 46 0 0 (set (reg:DI 64 0 [135])
                  (sign_extend:DI
                      (reg/v:SI 64 0 [orig:119 c ] [119])))
                   31 {extendsidi2} ...)

in try_replace_dest_reg, we updated the above EXPR_INSN_RTX to:

(insn 48 0 0 (set (reg:DI 32 0)
                  (sign_extend:DI
                      (reg/v:SI 64 0 [orig:119 c ] [119])))
                   31 {extendsidi2} ...)

The dest (reg 64) is a VR (also VSX REG), the updating makes
it become to (reg 32) which is a FPR (also VSX REG), we have
an alternative to match "VR,VR" but no one to match "FPR/VSX,
VR/VSX", so it fails with ICE.

This patch is to add the check before actually replacing dest
in expr with reg.

	PR rtl-optimization/112995

gcc/ChangeLog:

	* sel-sched.cc (try_replace_dest_reg): Check the validity of the
	replaced insn before actually replacing dest in expr.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/pr112995.c: New test.
---

diff --git a/gcc/sel-sched.cc b/gcc/sel-sched.cc
index 1925f4a9461c..a35b5e16c916 100644
--- a/gcc/sel-sched.cc
+++ b/gcc/sel-sched.cc
@@ -1614,7 +1614,15 @@ try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
   /* Make sure that EXPR has the right destination
      register.  */
   if (expr_dest_regno (expr) != REGNO (best_reg))
-    replace_dest_with_reg_in_expr (expr, best_reg);
+    {
+      rtx_insn *vinsn = EXPR_INSN_RTX (expr);
+      validate_change (vinsn, &SET_DEST (PATTERN (vinsn)), best_reg, 1);
+      bool res = verify_changes (0);
+      cancel_changes (0);
+      if (!res)
+	return false;
+      replace_dest_with_reg_in_expr (expr, best_reg);
+    }
   else
     EXPR_TARGET_AVAILABLE (expr) = 1;
 
diff --git a/gcc/testsuite/gcc.target/powerpc/pr112995.c b/gcc/testsuite/gcc.target/powerpc/pr112995.c
new file mode 100644
index 000000000000..4adcb5f38514
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr112995.c
@@ -0,0 +1,14 @@
+/* { dg-require-effective-target float128 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9 -fselective-scheduling2" } */
+
+/* Verify there is no ICE.  */
+
+int a[10];
+int b(_Float128 e) {
+  int c;
+  _Float128 d;
+  c = e;
+  d = c;
+  d = a[c] + d;
+  return d;
+}