From: Ville Syrjälä Date: Tue, 11 Feb 2025 23:19:29 +0000 (+0200) Subject: drm/i915: Bump RING_FAULT engine ID bits X-Git-Tag: v6.15-rc1~120^2^2~14 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=600a0c7e76bb28244e019da3d6a42cae0c836f60;p=thirdparty%2Fkernel%2Flinux.git drm/i915: Bump RING_FAULT engine ID bits The fault engine ID field has been 5 bits since icl. Bump our define to match. The extra bits were unused before icl so we should be able to use the larger mask unconditionally. Signed-off-by: Ville Syrjälä Reviewed-by: Andi Shyti Signed-off-by: Andi Shyti Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-2-ville.syrjala@linux.intel.com --- diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a6e50af44b465..424b7ff9dbf27 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1044,7 +1044,7 @@ #define GEN12_RING_FAULT_REG _MMIO(0xcec4) #define XEHP_RING_FAULT_REG MCR_REG(0xcec4) #define XELPMP_RING_FAULT_REG _MMIO(0xcec4) -#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) +#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x1f) #define RING_FAULT_GTTSEL_MASK (1 << 11) #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3)