From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Fri, 11 Jan 2019 12:40:17 +0000 (+0100)
Subject: 4.9-stable patches
X-Git-Tag: v4.20.2~17
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=60162f4017e2b07e1c6fe1114185823180c39df9;p=thirdparty%2Fkernel%2Fstable-queue.git

4.9-stable patches

added patches:
	iommu-vt-d-handle-domain-agaw-being-less-than-iommu-agaw.patch
---

diff --git a/queue-4.9/iommu-vt-d-handle-domain-agaw-being-less-than-iommu-agaw.patch b/queue-4.9/iommu-vt-d-handle-domain-agaw-being-less-than-iommu-agaw.patch
new file mode 100644
index 00000000000..157960cb6fe
--- /dev/null
+++ b/queue-4.9/iommu-vt-d-handle-domain-agaw-being-less-than-iommu-agaw.patch
@@ -0,0 +1,59 @@
+From 3569dd07aaad71920c5ea4da2d5cc9a167c1ffd4 Mon Sep 17 00:00:00 2001
+From: Sohil Mehta <sohil.mehta@intel.com>
+Date: Wed, 21 Nov 2018 15:29:33 -0800
+Subject: iommu/vt-d: Handle domain agaw being less than iommu agaw
+
+From: Sohil Mehta <sohil.mehta@intel.com>
+
+commit 3569dd07aaad71920c5ea4da2d5cc9a167c1ffd4 upstream.
+
+The Intel IOMMU driver opportunistically skips a few top level page
+tables from the domain paging directory while programming the IOMMU
+context entry. However there is an implicit assumption in the code that
+domain's adjusted guest address width (agaw) would always be greater
+than IOMMU's agaw.
+
+The IOMMU capabilities in an upcoming platform cause the domain's agaw
+to be lower than IOMMU's agaw. The issue is seen when the IOMMU supports
+both 4-level and 5-level paging. The domain builds a 4-level page table
+based on agaw of 2. However the IOMMU's agaw is set as 3 (5-level). In
+this case the code incorrectly tries to skip page page table levels.
+This causes the IOMMU driver to avoid programming the context entry. The
+fix handles this case and programs the context entry accordingly.
+
+Fixes: de24e55395698 ("iommu/vt-d: Simplify domain_context_mapping_one")
+Cc: <stable@vger.kernel.org>
+Cc: Ashok Raj <ashok.raj@intel.com>
+Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
+Cc: Lu Baolu <baolu.lu@linux.intel.com>
+Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>
+Reported-by: Ramos Falcon, Ernesto R <ernesto.r.ramos.falcon@intel.com>
+Tested-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
+Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/iommu/intel-iommu.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/iommu/intel-iommu.c
++++ b/drivers/iommu/intel-iommu.c
+@@ -2084,7 +2084,7 @@ static int domain_context_mapping_one(st
+ 	 * than default.  Unnecessary for PT mode.
+ 	 */
+ 	if (translation != CONTEXT_TT_PASS_THROUGH) {
+-		for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
++		for (agaw = domain->agaw; agaw > iommu->agaw; agaw--) {
+ 			ret = -ENOMEM;
+ 			pgd = phys_to_virt(dma_pte_addr(pgd));
+ 			if (!dma_pte_present(pgd))
+@@ -2098,7 +2098,7 @@ static int domain_context_mapping_one(st
+ 			translation = CONTEXT_TT_MULTI_LEVEL;
+ 
+ 		context_set_address_root(context, virt_to_phys(pgd));
+-		context_set_address_width(context, iommu->agaw);
++		context_set_address_width(context, agaw);
+ 	} else {
+ 		/*
+ 		 * In pass through mode, AW must be programmed to
diff --git a/queue-4.9/series b/queue-4.9/series
index dca29c0810e..26ec5ca1e0f 100644
--- a/queue-4.9/series
+++ b/queue-4.9/series
@@ -55,3 +55,4 @@ b43-fix-error-in-cordic-routine.patch
 powerpc-tm-set-msr-just-prior-to-recheckpoint.patch
 9p-net-put-a-lower-bound-on-msize.patch
 rxe-fix-error-completion-wr_id-and-qp_num.patch
+iommu-vt-d-handle-domain-agaw-being-less-than-iommu-agaw.patch