From: Peter Maydell Date: Tue, 29 Oct 2024 12:54:44 +0000 (+0000) Subject: docs/system/arm: Add placeholder doc for xlnx-zcu102 board X-Git-Tag: v9.2.0-rc0~29^2~5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=6128720af88eb9b5b3857f88785d32bc052049a7;p=thirdparty%2Fqemu.git docs/system/arm: Add placeholder doc for xlnx-zcu102 board Add a placeholder doc for the xlnx-zcu102 board. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Cédric Le Goater Reviewed-by: Alistair Francis Message-id: 20241018141332.942844-6-peter.maydell@linaro.org --- diff --git a/MAINTAINERS b/MAINTAINERS index 2b524d7af54..66c7572c27b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1018,6 +1018,7 @@ F: include/hw/ssi/xilinx_spips.h F: hw/display/dpcd.c F: include/hw/display/dpcd.h F: docs/system/arm/xlnx-versal-virt.rst +F: docs/system/arm/xlnx-zcu102.rst Xilinx Versal OSPI M: Francisco Iglesias diff --git a/docs/system/arm/xlnx-zcu102.rst b/docs/system/arm/xlnx-zcu102.rst new file mode 100644 index 00000000000..534cd1dc887 --- /dev/null +++ b/docs/system/arm/xlnx-zcu102.rst @@ -0,0 +1,19 @@ +Xilinx ZynqMP ZCU102 (``xlnx-zcu102``) +====================================== + +The ``xlnx-zcu102`` board models the Xilinx ZynqMP ZCU102 board. +This board has 4 Cortex-A53 CPUs and 2 Cortex-R5F CPUs. + +Machine-specific options +"""""""""""""""""""""""" + +The following machine-specific options are supported: + +secure + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Security Extensions (TrustZone). The default is ``off``. + +virtualization + Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the + Arm Virtualization Extensions. The default is ``off``. + diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index a7f88c8f317..ace36d1b17d 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -107,6 +107,7 @@ undocumented; you can get a complete list by running arm/xenpvh arm/xlnx-versal-virt arm/xlnx-zynq + arm/xlnx-zcu102 Emulated CPU architecture support =================================