From: Greg Kroah-Hartman Date: Mon, 2 May 2016 23:51:23 +0000 (-0700) Subject: 4.4-stable patches X-Git-Tag: v3.14.68~9 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=62bcff7015f2b23df1cb0da7535db84df048a6a3;p=thirdparty%2Fkernel%2Fstable-queue.git 4.4-stable patches added patches: arm-dts-armada-375-use-armada-370-sata-for-sata.patch arm-dts-pxa-fix-dma-engine-node-to-pxa3xx-nand.patch arm-exynos-select-thermal_of.patch arm-omap3-add-cpuidle-parameters-table-for-omap3430.patch arm-prima2-always-enable-reset-controller.patch bus-imx-weim-take-the-status-property-value-into-account.patch jme-do-not-enable-nic-wol-functions-on-s0.patch jme-fix-device-pm-wakeup-api-usage.patch --- diff --git a/queue-4.4/arm-dts-armada-375-use-armada-370-sata-for-sata.patch b/queue-4.4/arm-dts-armada-375-use-armada-370-sata-for-sata.patch new file mode 100644 index 00000000000..345ed1d6624 --- /dev/null +++ b/queue-4.4/arm-dts-armada-375-use-armada-370-sata-for-sata.patch @@ -0,0 +1,39 @@ +From b3a7f31eb7375633cd6a742f19488fc5a4208b36 Mon Sep 17 00:00:00 2001 +From: Lior Amsalem +Date: Wed, 10 Feb 2016 17:29:15 +0100 +Subject: ARM: dts: armada-375: use armada-370-sata for SATA + +From: Lior Amsalem + +commit b3a7f31eb7375633cd6a742f19488fc5a4208b36 upstream. + +The Armada 375 has the same SATA IP as Armada 370 and Armada XP, which +requires the PHY speed to be set in the LP_PHY_CTL register for SATA +hotplug to work. + +Therefore, this commit updates the compatible string used to describe +the SATA IP in Armada 375 from marvell,orion-sata to +marvell,armada-370-sata. + +Fixes: 4de59085091f753d08c8429d756b46756ab94665 ("ARM: mvebu: add Device Tree description of the Armada 375 SoC") +Signed-off-by: Lior Amsalem +Signed-off-by: Thomas Petazzoni +Reviewed-by: Andrew Lunn +Signed-off-by: Gregory CLEMENT +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/armada-375.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/armada-375.dtsi ++++ b/arch/arm/boot/dts/armada-375.dtsi +@@ -529,7 +529,7 @@ + }; + + sata@a0000 { +- compatible = "marvell,orion-sata"; ++ compatible = "marvell,armada-370-sata"; + reg = <0xa0000 0x5000>; + interrupts = ; + clocks = <&gateclk 14>, <&gateclk 20>; diff --git a/queue-4.4/arm-dts-pxa-fix-dma-engine-node-to-pxa3xx-nand.patch b/queue-4.4/arm-dts-pxa-fix-dma-engine-node-to-pxa3xx-nand.patch new file mode 100644 index 00000000000..b85749db42e --- /dev/null +++ b/queue-4.4/arm-dts-pxa-fix-dma-engine-node-to-pxa3xx-nand.patch @@ -0,0 +1,36 @@ +From 07c6b2d01d351f0512ed7145625265e435ab3240 Mon Sep 17 00:00:00 2001 +From: Robert Jarzmik +Date: Sat, 13 Feb 2016 00:49:20 +0100 +Subject: ARM: dts: pxa: fix dma engine node to pxa3xx-nand + +From: Robert Jarzmik + +commit 07c6b2d01d351f0512ed7145625265e435ab3240 upstream. + +Since the switch from mmp_pdma to pxa_dma driver for pxa architectures, +the pxa_dma requires 2 arguments, namely the requestor line and the +requested priority. + +Fix the only left device node which was still passing only one argument, +making the pxa3xx-nand driver misbehave in a device-tree configuration, +ie. failing all data transfers. + +Fixes: c943646d1f49 ("ARM: dts: pxa: add dma engine node to pxa3xx-nand") +Signed-off-by: Robert Jarzmik +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/pxa3xx.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/pxa3xx.dtsi ++++ b/arch/arm/boot/dts/pxa3xx.dtsi +@@ -30,7 +30,7 @@ + reg = <0x43100000 90>; + interrupts = <45>; + clocks = <&clks CLK_NAND>; +- dmas = <&pdma 97>; ++ dmas = <&pdma 97 3>; + dma-names = "data"; + #address-cells = <1>; + #size-cells = <1>; diff --git a/queue-4.4/arm-exynos-select-thermal_of.patch b/queue-4.4/arm-exynos-select-thermal_of.patch new file mode 100644 index 00000000000..5a9b5e20965 --- /dev/null +++ b/queue-4.4/arm-exynos-select-thermal_of.patch @@ -0,0 +1,38 @@ +From dc7eb9d589e595954792cc192bcbb92932e5c2ff Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Fri, 29 Jan 2016 15:50:38 +0100 +Subject: ARM: EXYNOS: select THERMAL_OF + +From: Arnd Bergmann + +commit dc7eb9d589e595954792cc192bcbb92932e5c2ff upstream. + +We cannot select a symbol that has disabled dependencies, so +we get a warning if we ever enable EXYNOS_THERMAL without +also turning on THERMAL_OF: + +warning: (ARCH_EXYNOS) selects EXYNOS_THERMAL which has unmet direct dependencies (THERMAL && (ARCH_EXYNOS || COMPILE_TEST) && THERMAL_OF) + +This adds another 'select' in the platform code to avoid that +case. Alternatively, we could decide to not select EXYNOS_THERMAL +here and instead make it a user option. + +Signed-off-by: Arnd Bergmann +Fixes: f87e6bd3f740 ("thermal: exynos: Add the dependency of CONFIG_THERMAL_OF instead of CONFIG_OF") +Signed-off-by: Krzysztof Kozlowski +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-exynos/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-exynos/Kconfig ++++ b/arch/arm/mach-exynos/Kconfig +@@ -26,6 +26,7 @@ menuconfig ARCH_EXYNOS + select S5P_DEV_MFC + select SRAM + select THERMAL ++ select THERMAL_OF + select MFD_SYSCON + help + Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5) diff --git a/queue-4.4/arm-omap3-add-cpuidle-parameters-table-for-omap3430.patch b/queue-4.4/arm-omap3-add-cpuidle-parameters-table-for-omap3430.patch new file mode 100644 index 00000000000..bc908c5c160 --- /dev/null +++ b/queue-4.4/arm-omap3-add-cpuidle-parameters-table-for-omap3430.patch @@ -0,0 +1,122 @@ +From 98f42221501353067251fbf11e732707dbb68ce3 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Fri, 19 Feb 2016 10:35:39 -0800 +Subject: ARM: OMAP3: Add cpuidle parameters table for omap3430 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +commit 98f42221501353067251fbf11e732707dbb68ce3 upstream. + +Based on CPU type choose generic omap3 or omap3430 specific cpuidle +parameters. Parameters for omap3430 were measured on Nokia N900 device and +added by commit 5a1b1d3a9efa ("OMAP3: RX-51: Pass cpu idle parameters") +which were later removed by commit 231900afba52 ("ARM: OMAP3: cpuidle - +remove rx51 cpuidle parameters table") due to huge code complexity. + +This patch brings cpuidle parameters for omap3430 devices again, but uses +simple condition based on CPU type. + +Fixes: 231900afba52 ("ARM: OMAP3: cpuidle - remove rx51 cpuidle +parameters table") +Signed-off-by: Pali Rohár +Acked-by: Daniel Lezcano +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-omap2/cpuidle34xx.c | 69 +++++++++++++++++++++++++++++++++++++- + 1 file changed, 68 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-omap2/cpuidle34xx.c ++++ b/arch/arm/mach-omap2/cpuidle34xx.c +@@ -34,6 +34,7 @@ + #include "pm.h" + #include "control.h" + #include "common.h" ++#include "soc.h" + + /* Mach specific information to be recorded in the C-state driver_data */ + struct omap3_idle_statedata { +@@ -315,6 +316,69 @@ static struct cpuidle_driver omap3_idle_ + .safe_state_index = 0, + }; + ++/* ++ * Numbers based on measurements made in October 2009 for PM optimized kernel ++ * with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP, ++ * and worst case latencies). ++ */ ++static struct cpuidle_driver omap3430_idle_driver = { ++ .name = "omap3430_idle", ++ .owner = THIS_MODULE, ++ .states = { ++ { ++ .enter = omap3_enter_idle_bm, ++ .exit_latency = 110 + 162, ++ .target_residency = 5, ++ .name = "C1", ++ .desc = "MPU ON + CORE ON", ++ }, ++ { ++ .enter = omap3_enter_idle_bm, ++ .exit_latency = 106 + 180, ++ .target_residency = 309, ++ .name = "C2", ++ .desc = "MPU ON + CORE ON", ++ }, ++ { ++ .enter = omap3_enter_idle_bm, ++ .exit_latency = 107 + 410, ++ .target_residency = 46057, ++ .name = "C3", ++ .desc = "MPU RET + CORE ON", ++ }, ++ { ++ .enter = omap3_enter_idle_bm, ++ .exit_latency = 121 + 3374, ++ .target_residency = 46057, ++ .name = "C4", ++ .desc = "MPU OFF + CORE ON", ++ }, ++ { ++ .enter = omap3_enter_idle_bm, ++ .exit_latency = 855 + 1146, ++ .target_residency = 46057, ++ .name = "C5", ++ .desc = "MPU RET + CORE RET", ++ }, ++ { ++ .enter = omap3_enter_idle_bm, ++ .exit_latency = 7580 + 4134, ++ .target_residency = 484329, ++ .name = "C6", ++ .desc = "MPU OFF + CORE RET", ++ }, ++ { ++ .enter = omap3_enter_idle_bm, ++ .exit_latency = 7505 + 15274, ++ .target_residency = 484329, ++ .name = "C7", ++ .desc = "MPU OFF + CORE OFF", ++ }, ++ }, ++ .state_count = ARRAY_SIZE(omap3_idle_data), ++ .safe_state_index = 0, ++}; ++ + /* Public functions */ + + /** +@@ -333,5 +397,8 @@ int __init omap3_idle_init(void) + if (!mpu_pd || !core_pd || !per_pd || !cam_pd) + return -ENODEV; + +- return cpuidle_register(&omap3_idle_driver, NULL); ++ if (cpu_is_omap3430()) ++ return cpuidle_register(&omap3430_idle_driver, NULL); ++ else ++ return cpuidle_register(&omap3_idle_driver, NULL); + } diff --git a/queue-4.4/arm-prima2-always-enable-reset-controller.patch b/queue-4.4/arm-prima2-always-enable-reset-controller.patch new file mode 100644 index 00000000000..b4e450875f9 --- /dev/null +++ b/queue-4.4/arm-prima2-always-enable-reset-controller.patch @@ -0,0 +1,40 @@ +From ef2b1d777d643af227a22309d8b79898b90b123c Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Sat, 28 Nov 2015 23:56:47 +0100 +Subject: ARM: prima2: always enable reset controller + +From: Arnd Bergmann + +commit ef2b1d777d643af227a22309d8b79898b90b123c upstream. + +The atlas7 clock controller driver registers a reset controller +for itself, which causes a link error when the subsystem is +disabled: + +drivers/built-in.o: In function `atlas7_clk_init': +drivers/clk/sirf/clk-atlas7.c:1681: undefined reference to `reset_controller_register' + +As the clk driver does not have a Kconfig symbol for itself +but it always built-in when the platform is enabled, we have +to ensure that the reset controller subsystem is also built-in +in this case. + +Signed-off-by: Arnd Bergmann +Acked-by: Philipp Zabel +Fixes: 301c5d29402e ("clk: sirf: add CSR atlas7 clk and reset support") +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-prima2/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-prima2/Kconfig ++++ b/arch/arm/mach-prima2/Kconfig +@@ -1,6 +1,7 @@ + menuconfig ARCH_SIRF + bool "CSR SiRF" if ARCH_MULTI_V7 + select ARCH_HAS_RESET_CONTROLLER ++ select RESET_CONTROLLER + select ARCH_REQUIRE_GPIOLIB + select GENERIC_IRQ_CHIP + select NO_IOPORT_MAP diff --git a/queue-4.4/bus-imx-weim-take-the-status-property-value-into-account.patch b/queue-4.4/bus-imx-weim-take-the-status-property-value-into-account.patch new file mode 100644 index 00000000000..eda2c81dc7c --- /dev/null +++ b/queue-4.4/bus-imx-weim-take-the-status-property-value-into-account.patch @@ -0,0 +1,58 @@ +From 33b96d2c9579213cf3f36d7b29841b1e464750c4 Mon Sep 17 00:00:00 2001 +From: Fabio Estevam +Date: Mon, 22 Feb 2016 09:01:53 -0300 +Subject: bus: imx-weim: Take the 'status' property value into account + +From: Fabio Estevam + +commit 33b96d2c9579213cf3f36d7b29841b1e464750c4 upstream. + +Currently we have an incorrect behaviour when multiple devices +are present under the weim node. For example: + +&weim { + ... + status = "okay"; + + sram@0,0 { + ... + status = "okay"; + }; + + mram@0,0 { + ... + status = "disabled"; + }; +}; + +In this case only the 'sram' device should be probed and not 'mram'. + +However what happens currently is that the status variable is ignored, +causing the 'sram' device to be disabled and 'mram' to be enabled. + +Change the weim_parse_dt() function to use +for_each_available_child_of_node()so that the devices marked with +'status = disabled' are not probed. + +Suggested-by: Wolfgang Netbal +Signed-off-by: Fabio Estevam +Reviewed-by: Sascha Hauer +Acked-by: Shawn Guo +Signed-off-by: Olof Johansson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/bus/imx-weim.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/bus/imx-weim.c ++++ b/drivers/bus/imx-weim.c +@@ -150,7 +150,7 @@ static int __init weim_parse_dt(struct p + return ret; + } + +- for_each_child_of_node(pdev->dev.of_node, child) { ++ for_each_available_child_of_node(pdev->dev.of_node, child) { + if (!child->name) + continue; + diff --git a/queue-4.4/jme-do-not-enable-nic-wol-functions-on-s0.patch b/queue-4.4/jme-do-not-enable-nic-wol-functions-on-s0.patch new file mode 100644 index 00000000000..ee94b784337 --- /dev/null +++ b/queue-4.4/jme-do-not-enable-nic-wol-functions-on-s0.patch @@ -0,0 +1,86 @@ +From 0772a99b818079e628a1da122ac7ee023faed83e Mon Sep 17 00:00:00 2001 +From: Guo-Fu Tseng +Date: Sat, 5 Mar 2016 08:11:55 +0800 +Subject: jme: Do not enable NIC WoL functions on S0 + +From: Guo-Fu Tseng + +commit 0772a99b818079e628a1da122ac7ee023faed83e upstream. + +Otherwise it might be back on resume right after going to suspend in +some hardware. + +Reported-by: Diego Viola +Signed-off-by: Guo-Fu Tseng +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/net/ethernet/jme.c | 17 +++++++++++------ + 1 file changed, 11 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/jme.c ++++ b/drivers/net/ethernet/jme.c +@@ -270,11 +270,17 @@ jme_reset_mac_processor(struct jme_adapt + } + + static inline void +-jme_clear_pm(struct jme_adapter *jme) ++jme_clear_pm_enable_wol(struct jme_adapter *jme) + { + jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs); + } + ++static inline void ++jme_clear_pm_disable_wol(struct jme_adapter *jme) ++{ ++ jwrite32(jme, JME_PMCS, PMCS_STMASK); ++} ++ + static int + jme_reload_eeprom(struct jme_adapter *jme) + { +@@ -1853,7 +1859,7 @@ jme_open(struct net_device *netdev) + struct jme_adapter *jme = netdev_priv(netdev); + int rc; + +- jme_clear_pm(jme); ++ jme_clear_pm_disable_wol(jme); + JME_NAPI_ENABLE(jme); + + tasklet_init(&jme->linkch_task, jme_link_change_tasklet, +@@ -1929,7 +1935,7 @@ jme_powersave_phy(struct jme_adapter *jm + jme_set_100m_half(jme); + if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN)) + jme_wait_link(jme); +- jme_clear_pm(jme); ++ jme_clear_pm_enable_wol(jme); + } else { + jme_phy_off(jme); + } +@@ -2646,7 +2652,6 @@ jme_set_wol(struct net_device *netdev, + if (wol->wolopts & WAKE_MAGIC) + jme->reg_pmcs |= PMCS_MFEN; + +- jwrite32(jme, JME_PMCS, jme->reg_pmcs); + device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs)); + + return 0; +@@ -3172,7 +3177,7 @@ jme_init_one(struct pci_dev *pdev, + jme->mii_if.mdio_read = jme_mdio_read; + jme->mii_if.mdio_write = jme_mdio_write; + +- jme_clear_pm(jme); ++ jme_clear_pm_disable_wol(jme); + device_set_wakeup_enable(&pdev->dev, true); + + jme_set_phyfifo_5level(jme); +@@ -3304,7 +3309,7 @@ jme_resume(struct device *dev) + if (!netif_running(netdev)) + return 0; + +- jme_clear_pm(jme); ++ jme_clear_pm_disable_wol(jme); + jme_phy_on(jme); + if (test_bit(JME_FLAG_SSET, &jme->flags)) + jme_set_settings(netdev, &jme->old_ecmd); diff --git a/queue-4.4/jme-fix-device-pm-wakeup-api-usage.patch b/queue-4.4/jme-fix-device-pm-wakeup-api-usage.patch new file mode 100644 index 00000000000..a4c9214c4f2 --- /dev/null +++ b/queue-4.4/jme-fix-device-pm-wakeup-api-usage.patch @@ -0,0 +1,58 @@ +From 81422e672f8181d7ad1ee6c60c723aac649f538f Mon Sep 17 00:00:00 2001 +From: Guo-Fu Tseng +Date: Sat, 5 Mar 2016 08:11:56 +0800 +Subject: jme: Fix device PM wakeup API usage + +From: Guo-Fu Tseng + +commit 81422e672f8181d7ad1ee6c60c723aac649f538f upstream. + +According to Documentation/power/devices.txt + +The driver should not use device_set_wakeup_enable() which is the policy +for user to decide. + +Using device_init_wakeup() to initialize dev->power.should_wakeup and +dev->power.can_wakeup on driver initialization. + +And use device_may_wakeup() on suspend to decide if WoL function should +be enabled on NIC. + +Reported-by: Diego Viola +Signed-off-by: Guo-Fu Tseng +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/net/ethernet/jme.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/jme.c ++++ b/drivers/net/ethernet/jme.c +@@ -1931,7 +1931,7 @@ jme_wait_link(struct jme_adapter *jme) + static void + jme_powersave_phy(struct jme_adapter *jme) + { +- if (jme->reg_pmcs) { ++ if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) { + jme_set_100m_half(jme); + if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN)) + jme_wait_link(jme); +@@ -2652,8 +2652,6 @@ jme_set_wol(struct net_device *netdev, + if (wol->wolopts & WAKE_MAGIC) + jme->reg_pmcs |= PMCS_MFEN; + +- device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs)); +- + return 0; + } + +@@ -3178,7 +3176,7 @@ jme_init_one(struct pci_dev *pdev, + jme->mii_if.mdio_write = jme_mdio_write; + + jme_clear_pm_disable_wol(jme); +- device_set_wakeup_enable(&pdev->dev, true); ++ device_init_wakeup(&pdev->dev, true); + + jme_set_phyfifo_5level(jme); + jme->pcirev = pdev->revision; diff --git a/queue-4.4/series b/queue-4.4/series index ca46827d2f1..f451388355a 100644 --- a/queue-4.4/series +++ b/queue-4.4/series @@ -147,3 +147,11 @@ ext4-fix-races-between-page-faults-and-hole-punching.patch ext4-move-unlocked-dio-protection-from-ext4_alloc_file_blocks.patch ext4-fix-races-between-buffered-io-and-collapse-insert-range.patch ext4-fix-races-of-writeback-with-punch-hole-and-zero-range.patch +arm-omap3-add-cpuidle-parameters-table-for-omap3430.patch +arm-prima2-always-enable-reset-controller.patch +arm-exynos-select-thermal_of.patch +arm-dts-armada-375-use-armada-370-sata-for-sata.patch +arm-dts-pxa-fix-dma-engine-node-to-pxa3xx-nand.patch +bus-imx-weim-take-the-status-property-value-into-account.patch +jme-do-not-enable-nic-wol-functions-on-s0.patch +jme-fix-device-pm-wakeup-api-usage.patch