From: Peter Maydell <peter.maydell@linaro.org>
Date: Mon, 18 May 2015 19:23:16 +0000 (+0100)
Subject: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150518-3' into... 
X-Git-Tag: v2.4.0-rc0~131
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=62bf3df432d93fa6eb0f355c460d6d784b7cbc1a;p=thirdparty%2Fqemu.git

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150518-3' into staging

target-arm:
 * New board model: xlnx-ep108
 * Some more preparation for AArch64 EL2/EL3
 * Fix bugs in access checking for generic counter registers
 * Remove a stray '+' sign

# gpg: Signature made Mon May 18 20:13:05 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20150518-3: (21 commits)
  target-arm: Remove unneeded '+'
  target-arm: Correct accessfn for CNTV_TVAL_EL0
  target-arm: Correct accessfn for CNTP_{CT}VAL_EL0
  target-arm: Add WFx syndrome function
  target-arm: Add EL3 and EL2 TCR checking
  target-arm: Add TTBR regime function and use
  linux-user/arm: Correct TARGET_NR_timerfd to TARGET_NR_timerfd_create
  arm: xlnx-ep108: Add bootloading
  arm: xlnx-ep108: Add external RAM
  arm: Add xlnx-ep108 machine
  arm: xlnx-zynqmp: Add UART support
  char: cadence_uart: Split state struct and type into header
  char: cadence_uart: Clean up variable names
  arm: xlnx-zynqmp: Add GEM support
  net: cadence_gem: Split state struct and type into header
  net: cadence_gem: Clean up variable names
  arm: xlnx-zynqmp: Connect CPU Timers to GIC
  arm: xlnx-zynqmp: Add GIC
  arm: Introduce Xilinx ZynqMP SoC
  target-arm: cpu64: Add support for Cortex-A53
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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62bf3df432d93fa6eb0f355c460d6d784b7cbc1a