From: Jan Beulich <jbeulich@suse.com>
Date: Fri, 19 Jan 2024 09:19:15 +0000 (+0100)
Subject: x86-64: Dwarf2 register numbers for %bnd<N>
X-Git-Tag: gdb-15-branchpoint~1209
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=633789901c83;p=thirdparty%2Fbinutils-gdb.git

x86-64: Dwarf2 register numbers for %bnd<N>

I don't see why we shouldn't record them when they have been allocated,
even if they're (bogusly) named as reserved in the ABI right now.
---

diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index f92315392b8..87d2665243d 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -353,10 +353,10 @@ tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
 tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
 tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
 // Bound registers for MPX
-bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
-bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
-bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
-bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
+bnd0, Class=RegBND, 0, 0, Dw2Inval, 126
+bnd1, Class=RegBND, 0, 1, Dw2Inval, 127
+bnd2, Class=RegBND, 0, 2, Dw2Inval, 128
+bnd3, Class=RegBND, 0, 3, Dw2Inval, 129
 // No Class=Reg will make these registers rejected for all purposes except
 // for addressing.  This saves creating one extra type for RIP/EIP.
 rip, Qword, RegRex64, RegIP, Dw2Inval, 16
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 72d5b9fbcf7..bdcc3c86b50 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -44881,19 +44881,19 @@ static const reg_entry i386_regtab[] =
   { "bnd0",
     { { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0 } },
-    0, 0, { Dw2Inval, Dw2Inval } },
+    0, 0, { Dw2Inval, 126 } },
   { "bnd1",
     { { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0 } },
-    0, 1, { Dw2Inval, Dw2Inval } },
+    0, 1, { Dw2Inval, 127 } },
   { "bnd2",
     { { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0 } },
-    0, 2, { Dw2Inval, Dw2Inval } },
+    0, 2, { Dw2Inval, 128 } },
   { "bnd3",
     { { 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0 } },
-    0, 3, { Dw2Inval, Dw2Inval } },
+    0, 3, { Dw2Inval, 129 } },
   { "rip",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
 	0, 0, 0, 0, 0, 0 } },