From: Li Xu <xuli1@eswincomputing.com>
Date: Mon, 3 Apr 2023 03:58:52 +0000 (-0600)
Subject: RISC-V: Fix typo
X-Git-Tag: basepoints/gcc-14~225
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=63e95a83cedd95e4b054dbd602082b0622e55a33;p=thirdparty%2Fgcc.git

RISC-V: Fix typo

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins.def (vuint32m8_t): Fix typo.
	(vfloat32m8_t): Likewise
---

diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index d4a74befd8a4..2d527f76f0af 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -234,7 +234,7 @@ DEF_RVV_TYPE (vuint32m8_t, 16, __rvv_uint32m8_t, uint32, VNx16SI, VNx8SI,
 	      _u32m8, _u32, _e32m8)
 
 /* SEW = 64:
-   Disable when TARGET_MIN_VLEN > 32.  */
+   Enable when TARGET_MIN_VLEN > 32.  */
 DEF_RVV_TYPE (vint64m1_t, 15, __rvv_int64m1_t, int64, VNx1DI, VOID, _i64m1,
 	      _i64, _e64m1)
 DEF_RVV_TYPE (vuint64m1_t, 16, __rvv_uint64m1_t, uint64, VNx1DI, VOID, _u64m1,
@@ -278,7 +278,7 @@ DEF_RVV_TYPE (vfloat32m8_t, 17, __rvv_float32m8_t, float, VNx16SF, VNx8SF,
 	      _f32m8, _f32, _e32m8)
 
 /* SEW = 64:
-   Disable when TARGET_VECTOR_FP64.  */
+   Enable when TARGET_VECTOR_FP64.  */
 DEF_RVV_TYPE (vfloat64m1_t, 17, __rvv_float64m1_t, double, VNx1DF, VOID, _f64m1,
 	      _f64, _e64m1)
 DEF_RVV_TYPE (vfloat64m2_t, 17, __rvv_float64m2_t, double, VNx2DF, VOID, _f64m2,