From: Sasha Levin Date: Mon, 7 Feb 2022 02:13:23 +0000 (-0500) Subject: Fixes for 5.15 X-Git-Tag: v4.9.300~18 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=647a19432310bc72d28465600e2f22ec4d5b7ba7;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.15 Signed-off-by: Sasha Levin --- diff --git a/queue-5.15/kvm-arm64-rework-guest-entry-logic.patch b/queue-5.15/kvm-arm64-rework-guest-entry-logic.patch new file mode 100644 index 00000000000..aef3a6f4edd --- /dev/null +++ b/queue-5.15/kvm-arm64-rework-guest-entry-logic.patch @@ -0,0 +1,142 @@ +From f0fe79210d509bbb2a9779b11143bce67cd2bd5e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 1 Feb 2022 13:29:23 +0000 +Subject: kvm/arm64: rework guest entry logic + +From: Mark Rutland + +[ Upstream commit 8cfe148a7136bc60452a5c6b7ac2d9d15c36909b ] + +In kvm_arch_vcpu_ioctl_run() we enter an RCU extended quiescent state +(EQS) by calling guest_enter_irqoff(), and unmasked IRQs prior to +exiting the EQS by calling guest_exit(). As the IRQ entry code will not +wake RCU in this case, we may run the core IRQ code and IRQ handler +without RCU watching, leading to various potential problems. + +Additionally, we do not inform lockdep or tracing that interrupts will +be enabled during guest execution, which caan lead to misleading traces +and warnings that interrupts have been enabled for overly-long periods. + +This patch fixes these issues by using the new timing and context +entry/exit helpers to ensure that interrupts are handled during guest +vtime but with RCU watching, with a sequence: + + guest_timing_enter_irqoff(); + + guest_state_enter_irqoff(); + < run the vcpu > + guest_state_exit_irqoff(); + + < take any pending IRQs > + + guest_timing_exit_irqoff(); + +Since instrumentation may make use of RCU, we must also ensure that no +instrumented code is run during the EQS. I've split out the critical +section into a new kvm_arm_enter_exit_vcpu() helper which is marked +noinstr. + +Fixes: 1b3d546daf85ed2b ("arm/arm64: KVM: Properly account for guest CPU time") +Reported-by: Nicolas Saenz Julienne +Signed-off-by: Mark Rutland +Reviewed-by: Marc Zyngier +Reviewed-by: Nicolas Saenz Julienne +Cc: Alexandru Elisei +Cc: Catalin Marinas +Cc: Frederic Weisbecker +Cc: James Morse +Cc: Paolo Bonzini +Cc: Paul E. McKenney +Cc: Suzuki K Poulose +Cc: Will Deacon +Message-Id: <20220201132926.3301912-3-mark.rutland@arm.com> +Signed-off-by: Paolo Bonzini +Signed-off-by: Sasha Levin +--- + arch/arm64/kvm/arm.c | 51 ++++++++++++++++++++++++++++---------------- + 1 file changed, 33 insertions(+), 18 deletions(-) + +diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c +index 9b328bb05596a..f9c7e4e61b296 100644 +--- a/arch/arm64/kvm/arm.c ++++ b/arch/arm64/kvm/arm.c +@@ -755,6 +755,24 @@ static bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu, int *ret) + xfer_to_guest_mode_work_pending(); + } + ++/* ++ * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while ++ * the vCPU is running. ++ * ++ * This must be noinstr as instrumentation may make use of RCU, and this is not ++ * safe during the EQS. ++ */ ++static int noinstr kvm_arm_vcpu_enter_exit(struct kvm_vcpu *vcpu) ++{ ++ int ret; ++ ++ guest_state_enter_irqoff(); ++ ret = kvm_call_hyp_ret(__kvm_vcpu_run, vcpu); ++ guest_state_exit_irqoff(); ++ ++ return ret; ++} ++ + /** + * kvm_arch_vcpu_ioctl_run - the main VCPU run function to execute guest code + * @vcpu: The VCPU pointer +@@ -845,9 +863,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) + * Enter the guest + */ + trace_kvm_entry(*vcpu_pc(vcpu)); +- guest_enter_irqoff(); ++ guest_timing_enter_irqoff(); + +- ret = kvm_call_hyp_ret(__kvm_vcpu_run, vcpu); ++ ret = kvm_arm_vcpu_enter_exit(vcpu); + + vcpu->mode = OUTSIDE_GUEST_MODE; + vcpu->stat.exits++; +@@ -882,26 +900,23 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) + kvm_arch_vcpu_ctxsync_fp(vcpu); + + /* +- * We may have taken a host interrupt in HYP mode (ie +- * while executing the guest). This interrupt is still +- * pending, as we haven't serviced it yet! ++ * We must ensure that any pending interrupts are taken before ++ * we exit guest timing so that timer ticks are accounted as ++ * guest time. Transiently unmask interrupts so that any ++ * pending interrupts are taken. + * +- * We're now back in SVC mode, with interrupts +- * disabled. Enabling the interrupts now will have +- * the effect of taking the interrupt again, in SVC +- * mode this time. ++ * Per ARM DDI 0487G.b section D1.13.4, an ISB (or other ++ * context synchronization event) is necessary to ensure that ++ * pending interrupts are taken. + */ + local_irq_enable(); ++ isb(); ++ local_irq_disable(); ++ ++ guest_timing_exit_irqoff(); ++ ++ local_irq_enable(); + +- /* +- * We do local_irq_enable() before calling guest_exit() so +- * that if a timer interrupt hits while running the guest we +- * account that tick as being spent in the guest. We enable +- * preemption after calling guest_exit() so that if we get +- * preempted we make sure ticks after that is not counted as +- * guest time. +- */ +- guest_exit(); + trace_kvm_exit(ret, kvm_vcpu_trap_get_class(vcpu), *vcpu_pc(vcpu)); + + /* Exit types that need handling before we can be preempted */ +-- +2.34.1 + diff --git a/queue-5.15/perf-copy-perf_event_attr-sig_data-on-modification.patch b/queue-5.15/perf-copy-perf_event_attr-sig_data-on-modification.patch new file mode 100644 index 00000000000..f5aec697263 --- /dev/null +++ b/queue-5.15/perf-copy-perf_event_attr-sig_data-on-modification.patch @@ -0,0 +1,73 @@ +From 7f91eff84f27e598f934292adebb451aa15d1552 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 31 Jan 2022 11:34:05 +0100 +Subject: perf: Copy perf_event_attr::sig_data on modification + +From: Marco Elver + +[ Upstream commit 3c25fc97f5590060464cabfa25710970ecddbc96 ] + +The intent has always been that perf_event_attr::sig_data should also be +modifiable along with PERF_EVENT_IOC_MODIFY_ATTRIBUTES, because it is +observable by user space if SIGTRAP on events is requested. + +Currently only PERF_TYPE_BREAKPOINT is modifiable, and explicitly copies +relevant breakpoint-related attributes in hw_breakpoint_copy_attr(). +This misses copying perf_event_attr::sig_data. + +Since sig_data is not specific to PERF_TYPE_BREAKPOINT, introduce a +helper to copy generic event-type-independent attributes on +modification. + +Fixes: 97ba62b27867 ("perf: Add support for SIGTRAP on perf events") +Reported-by: Dmitry Vyukov +Signed-off-by: Marco Elver +Signed-off-by: Peter Zijlstra (Intel) +Reviewed-by: Dmitry Vyukov +Link: https://lore.kernel.org/r/20220131103407.1971678-1-elver@google.com +Signed-off-by: Sasha Levin +--- + kernel/events/core.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/kernel/events/core.c b/kernel/events/core.c +index c7581e3fb8ab1..69c70767b5dff 100644 +--- a/kernel/events/core.c ++++ b/kernel/events/core.c +@@ -3234,6 +3234,15 @@ static int perf_event_modify_breakpoint(struct perf_event *bp, + return err; + } + ++/* ++ * Copy event-type-independent attributes that may be modified. ++ */ ++static void perf_event_modify_copy_attr(struct perf_event_attr *to, ++ const struct perf_event_attr *from) ++{ ++ to->sig_data = from->sig_data; ++} ++ + static int perf_event_modify_attr(struct perf_event *event, + struct perf_event_attr *attr) + { +@@ -3256,10 +3265,17 @@ static int perf_event_modify_attr(struct perf_event *event, + WARN_ON_ONCE(event->ctx->parent_ctx); + + mutex_lock(&event->child_mutex); ++ /* ++ * Event-type-independent attributes must be copied before event-type ++ * modification, which will validate that final attributes match the ++ * source attributes after all relevant attributes have been copied. ++ */ ++ perf_event_modify_copy_attr(&event->attr, attr); + err = func(event, attr); + if (err) + goto out; + list_for_each_entry(child, &event->child_list, child_list) { ++ perf_event_modify_copy_attr(&child->attr, attr); + err = func(child, attr); + if (err) + goto out; +-- +2.34.1 + diff --git a/queue-5.15/perf-stat-fix-display-of-grouped-aliased-events.patch b/queue-5.15/perf-stat-fix-display-of-grouped-aliased-events.patch new file mode 100644 index 00000000000..26347be5186 --- /dev/null +++ b/queue-5.15/perf-stat-fix-display-of-grouped-aliased-events.patch @@ -0,0 +1,256 @@ +From 215d40f8a60d8b60a6fd5fd719c43c9b91db0487 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 4 Feb 2022 17:09:41 -0800 +Subject: perf stat: Fix display of grouped aliased events + +From: Ian Rogers + +[ Upstream commit b2b1aa73ade982c175ac926a1fd34e76ad628b94 ] + +An event may have a number of uncore aliases that when added to the +evlist are consecutive. + +If there are multiple uncore events in a group then +parse_events__set_leader_for_uncore_aliase will reorder the evlist so +that events on the same PMU are adjacent. + +The collect_all_aliases function assumes that aliases are in blocks so +that only the first counter is printed and all others are marked merged. + +The reordering for groups breaks the assumption and so all counts are +printed. + +This change removes the assumption from collect_all_aliases +that the events are in blocks and instead processes the entire evlist. + +Before: + + ``` + $ perf stat -e '{UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE,UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE},duration_time' -a -A -- sleep 1 + + Performance counter stats for 'system wide': + + CPU0 256,866 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 494,413 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 967 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,738 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 285,161 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 429,920 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 955 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,443 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 310,753 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 416,657 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,231 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,573 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 416,067 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 405,966 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,481 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,447 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 312,911 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 408,154 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,086 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,380 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 333,994 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 370,349 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,287 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,335 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 188,107 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 302,423 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 701 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,070 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 307,221 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 383,642 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,036 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,158 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 318,479 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 821,545 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,028 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 2,550 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 227,618 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 372,272 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 903 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,456 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 376,783 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 419,827 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,406 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,453 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 286,583 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 429,956 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 999 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,436 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 313,867 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 370,159 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,114 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,291 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 342,083 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 409,111 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,399 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,684 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 365,828 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 376,037 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,378 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,411 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 382,456 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 621,743 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,232 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,955 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 342,316 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 385,067 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,176 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,268 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 373,588 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 386,163 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,394 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,464 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 381,206 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 546,891 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,266 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,712 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 221,176 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 392,069 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 831 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,456 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 355,401 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 705,595 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,235 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 2,216 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 371,436 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 428,103 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,306 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,442 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 384,352 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 504,200 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,468 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,860 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 228,856 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 287,976 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 832 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,060 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 215,121 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 334,162 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 681 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,026 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 296,179 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 436,083 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,084 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,525 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 262,296 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 416,573 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 986 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,533 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 285,852 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 359,842 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,073 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,326 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 303,379 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 367,222 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,008 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,156 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 273,487 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 425,449 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 932 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,367 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 297,596 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 414,793 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,140 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,601 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 342,365 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 360,422 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,291 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,342 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 327,196 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 580,858 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,122 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 2,014 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 296,564 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 452,817 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,087 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,694 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 375,002 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 389,393 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,478 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 1,540 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 365,213 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 594,685 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 1,401 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 2,222 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 1,000,749,060 ns duration_time + + 1.000749060 seconds time elapsed + ``` + +After: + + ``` + Performance counter stats for 'system wide': + + CPU0 20,547,434 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU36 45,202,862 UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE + CPU0 82,001 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU36 159,688 UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + CPU0 1,000,464,828 ns duration_time + + 1.000464828 seconds time elapsed + ``` + +Fixes: 3cdc5c2cb924acb4 ("perf parse-events: Handle uncore event aliases in small groups properly") +Reviewed-by: Andi Kleen +Signed-off-by: Ian Rogers +Cc: Alexander Shishkin +Cc: Alexandre Torgue +Cc: Asaf Yaffe +Cc: Caleb Biggers +Cc: Ingo Molnar +Cc: James Clark +Cc: Jiri Olsa +Cc: John Garry +Cc: Kan Liang +Cc: Kshipra Bopardikar +Cc: Mark Rutland +Cc: Maxime Coquelin +Cc: Namhyung Kim +Cc: Perry Taylor +Cc: Peter Zijlstra +Cc: Stephane Eranian +Cc: Vineet Singh +Cc: Zhengjun Xing +Link: https://lore.kernel.org/r/20220205010941.1065469-1-irogers@google.com +Signed-off-by: Arnaldo Carvalho de Melo +Signed-off-by: Sasha Levin +--- + tools/perf/util/stat-display.c | 19 ++++++++++--------- + 1 file changed, 10 insertions(+), 9 deletions(-) + +diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c +index 588601000f3f9..db00ca6a67deb 100644 +--- a/tools/perf/util/stat-display.c ++++ b/tools/perf/util/stat-display.c +@@ -584,15 +584,16 @@ static void collect_all_aliases(struct perf_stat_config *config, struct evsel *c + + alias = list_prepare_entry(counter, &(evlist->core.entries), core.node); + list_for_each_entry_continue (alias, &evlist->core.entries, core.node) { +- if (strcmp(evsel__name(alias), evsel__name(counter)) || +- alias->scale != counter->scale || +- alias->cgrp != counter->cgrp || +- strcmp(alias->unit, counter->unit) || +- evsel__is_clock(alias) != evsel__is_clock(counter) || +- !strcmp(alias->pmu_name, counter->pmu_name)) +- break; +- alias->merged_stat = true; +- cb(config, alias, data, false); ++ /* Merge events with the same name, etc. but on different PMUs. */ ++ if (!strcmp(evsel__name(alias), evsel__name(counter)) && ++ alias->scale == counter->scale && ++ alias->cgrp == counter->cgrp && ++ !strcmp(alias->unit, counter->unit) && ++ evsel__is_clock(alias) == evsel__is_clock(counter) && ++ strcmp(alias->pmu_name, counter->pmu_name)) { ++ alias->merged_stat = true; ++ cb(config, alias, data, false); ++ } + } + } + +-- +2.34.1 + diff --git a/queue-5.15/series b/queue-5.15/series index 01f62aa6fbe..c7ae5394d21 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -89,3 +89,6 @@ selftests-futex-use-variable-make-instead-of-make.patch tools-resolve_btfids-do-not-print-any-commands-when-building-silently.patch e1000e-separate-adp-board-type-from-tgp.patch rtc-cmos-evaluate-century-appropriate.patch +kvm-arm64-rework-guest-entry-logic.patch +perf-copy-perf_event_attr-sig_data-on-modification.patch +perf-stat-fix-display-of-grouped-aliased-events.patch