From: Karel Zak Date: Mon, 17 Mar 2025 10:03:52 +0000 (+0100) Subject: tests: (lscpu) update RISC-V tests to add ISA line X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=659dcaa76fae256de9323b00d40cd6b0df61ff6d;p=thirdparty%2Futil-linux.git tests: (lscpu) update RISC-V tests to add ISA line Signed-off-by: Karel Zak --- diff --git a/tests/expected/lscpu/lscpu-rv64-linux b/tests/expected/lscpu/lscpu-rv64-linux index d741cae22..fbfea0b4f 100644 --- a/tests/expected/lscpu/lscpu-rv64-linux +++ b/tests/expected/lscpu/lscpu-rv64-linux @@ -4,6 +4,7 @@ Model name: sifive,u74-mc Thread(s) per core: 2 Core(s) per socket: 1 Socket(s): 1 +ISA: rv64imafdc L1d cache: 64 KiB (2 instances) L1i cache: 64 KiB (2 instances) L2 cache: 2 MiB (1 instance) diff --git a/tests/expected/lscpu/lscpu-rv64-milkvpioneer b/tests/expected/lscpu/lscpu-rv64-milkvpioneer index 8345664d8..69a574b97 100644 --- a/tests/expected/lscpu/lscpu-rv64-milkvpioneer +++ b/tests/expected/lscpu/lscpu-rv64-milkvpioneer @@ -7,6 +7,7 @@ Model: 0x0 Thread(s) per core: 1 Core(s) per socket: 64 Socket(s): 1 +ISA: rv64imafdcv NUMA node(s): 4 NUMA node0 CPU(s): 0-7,16-23 NUMA node1 CPU(s): 8-15,24-31 diff --git a/tests/expected/lscpu/lscpu-rv64-visionfive2 b/tests/expected/lscpu/lscpu-rv64-visionfive2 index 0b2390d88..cd87ba57b 100644 --- a/tests/expected/lscpu/lscpu-rv64-visionfive2 +++ b/tests/expected/lscpu/lscpu-rv64-visionfive2 @@ -8,6 +8,7 @@ Model: 0x4210427 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 +ISA: rv64imafdc zba zbb zicntr zicsr zifencei zihpm L1d cache: 128 KiB (4 instances) L1i cache: 128 KiB (4 instances) L2 cache: 2 MiB (1 instance)