From: qizhong cheng Date: Mon, 27 Dec 2021 13:31:10 +0000 (+0800) Subject: PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize X-Git-Tag: v5.17-rc1~73^2~12^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=65ace9a85fa7f88aec4d9d842061108161fa47bc;p=thirdparty%2Fkernel%2Flinux.git PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com Signed-off-by: qizhong cheng Signed-off-by: Lorenzo Pieralisi Acked-by: Pali Rohár --- diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c index 2f3f974977a36..b18935e8da89a 100644 --- a/drivers/pci/controller/pcie-mediatek.c +++ b/drivers/pci/controller/pcie-mediatek.c @@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) */ writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); + /* + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should + * be delayed 100ms (TPVPERL) for the power and clock to become stable. + */ + msleep(100); + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ val = readl(port->base + PCIE_RST_CTRL); val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |