From: Bastian Koppelmann Date: Thu, 2 Feb 2023 12:04:23 +0000 (+0100) Subject: target/tricore: Fix OPC2_32_RCRW_IMASK translation X-Git-Tag: v8.0.0-rc0~65^2~11 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=65e57fdb25a0df8950f107041550aeb178af41ad;p=thirdparty%2Fqemu.git target/tricore: Fix OPC2_32_RCRW_IMASK translation we were mixing up the "c" and "d" registers. We used "d" as a destination register und "c" as the source. According to the TriCore ISA manual 1.6 vol 2 it is the other way round. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653 Message-Id: <20230202120432.1268-2-kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann --- diff --git a/target/tricore/translate.c b/target/tricore/translate.c index df9e46c6495..8de4e56b1f1 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -5794,11 +5794,11 @@ static void decode_rcrw_insert(DisasContext *ctx) switch (op2) { case OPC2_32_RCRW_IMASK: - tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); + tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); tcg_gen_movi_tl(temp2, (1 << width) - 1); - tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); + tcg_gen_shl_tl(cpu_gpr_d[r4 + 1], temp2, temp); tcg_gen_movi_tl(temp2, const4); - tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); + tcg_gen_shl_tl(cpu_gpr_d[r4], temp2, temp); break; case OPC2_32_RCRW_INSERT: temp3 = tcg_temp_new();