From: Greg Kroah-Hartman Date: Sun, 23 Jan 2022 17:04:35 +0000 (+0100) Subject: 5.4-stable patches X-Git-Tag: v4.4.300~112 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=66349408edddc225a2e328bd4ff0fcbf3359d094;p=thirdparty%2Fkernel%2Fstable-queue.git 5.4-stable patches added patches: pci-pci-bridge-emul-correctly-set-pcie-capabilities.patch pci-pci-bridge-emul-properly-mark-reserved-pcie-bits-in-pci-config-space.patch pci-pci-bridge-emul-set-pci_status_cap_list-for-pcie-device.patch pci-pciehp-fix-infinite-loop-in-irq-handler-upon-power-fault.patch xfrm-fix-policy-lookup-for-ipv6-gre-packets.patch --- diff --git a/queue-5.4/pci-pci-bridge-emul-correctly-set-pcie-capabilities.patch b/queue-5.4/pci-pci-bridge-emul-correctly-set-pcie-capabilities.patch new file mode 100644 index 00000000000..21107cb6596 --- /dev/null +++ b/queue-5.4/pci-pci-bridge-emul-correctly-set-pcie-capabilities.patch @@ -0,0 +1,89 @@ +From 1f1050c5e1fefb34ac90a506b43e9da803b5f8f7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Wed, 24 Nov 2021 16:59:43 +0100 +Subject: PCI: pci-bridge-emul: Correctly set PCIe capabilities +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +commit 1f1050c5e1fefb34ac90a506b43e9da803b5f8f7 upstream. + +Older mvebu hardware provides PCIe Capability structure only in version 1. +New mvebu and aardvark hardware provides it in version 2. So do not force +version to 2 in pci_bridge_emul_init() and rather allow drivers to set +correct version. Drivers need to set version in pcie_conf.cap field without +overwriting PCI_CAP_LIST_ID register. Both drivers (mvebu and aardvark) do +not provide slot support yet, so do not set PCI_EXP_FLAGS_SLOT flag. + +Link: https://lore.kernel.org/r/20211124155944.1290-6-pali@kernel.org +Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic") +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pci-aardvark.c | 4 +++- + drivers/pci/controller/pci-mvebu.c | 8 ++++++++ + drivers/pci/pci-bridge-emul.c | 5 +---- + 3 files changed, 12 insertions(+), 5 deletions(-) + +--- a/drivers/pci/controller/pci-aardvark.c ++++ b/drivers/pci/controller/pci-aardvark.c +@@ -863,7 +863,6 @@ advk_pci_bridge_emul_pcie_conf_read(stru + return PCI_BRIDGE_EMUL_HANDLED; + } + +- case PCI_CAP_LIST_ID: + case PCI_EXP_DEVCAP: + case PCI_EXP_DEVCTL: + *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); +@@ -944,6 +943,9 @@ static int advk_sw_pci_bridge_init(struc + /* Support interrupt A for MSI feature */ + bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; + ++ /* Aardvark HW provides PCIe Capability structure in version 2 */ ++ bridge->pcie_conf.cap = cpu_to_le16(2); ++ + /* Indicates supports for Completion Retry Status */ + bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); + +--- a/drivers/pci/controller/pci-mvebu.c ++++ b/drivers/pci/controller/pci-mvebu.c +@@ -576,6 +576,8 @@ struct pci_bridge_emul_ops mvebu_pci_bri + static void mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port) + { + struct pci_bridge_emul *bridge = &port->bridge; ++ u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP); ++ u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS); + + bridge->conf.vendor = PCI_VENDOR_ID_MARVELL; + bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; +@@ -588,6 +590,12 @@ static void mvebu_pci_bridge_emul_init(s + bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; + } + ++ /* ++ * Older mvebu hardware provides PCIe Capability structure only in ++ * version 1. New hardware provides it in version 2. ++ */ ++ bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver); ++ + bridge->has_pcie = true; + bridge->data = port; + bridge->ops = &mvebu_pci_bridge_emul_ops; +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -288,10 +288,7 @@ int pci_bridge_emul_init(struct pci_brid + if (bridge->has_pcie) { + bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START; + bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP; +- /* Set PCIe v2, root port, slot support */ +- bridge->pcie_conf.cap = +- cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4 | 2 | +- PCI_EXP_FLAGS_SLOT); ++ bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4); + bridge->pcie_cap_regs_behavior = + kmemdup(pcie_cap_regs_behavior, + sizeof(pcie_cap_regs_behavior), diff --git a/queue-5.4/pci-pci-bridge-emul-properly-mark-reserved-pcie-bits-in-pci-config-space.patch b/queue-5.4/pci-pci-bridge-emul-properly-mark-reserved-pcie-bits-in-pci-config-space.patch new file mode 100644 index 00000000000..3d6014fedb2 --- /dev/null +++ b/queue-5.4/pci-pci-bridge-emul-properly-mark-reserved-pcie-bits-in-pci-config-space.patch @@ -0,0 +1,56 @@ +From 7b067ac63a5730d2fae18399fed7e45f23d36912 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Wed, 24 Nov 2021 16:59:40 +0100 +Subject: PCI: pci-bridge-emul: Properly mark reserved PCIe bits in PCI config space +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +commit 7b067ac63a5730d2fae18399fed7e45f23d36912 upstream. + +Some bits in PCI config space are reserved when device is PCIe. Properly +define behavior of PCI registers for PCIe emulated bridge and ensure that +it would not be possible change these reserved bits. + +Link: https://lore.kernel.org/r/20211124155944.1290-3-pali@kernel.org +Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic") +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/pci-bridge-emul.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -300,6 +300,27 @@ int pci_bridge_emul_init(struct pci_brid + kfree(bridge->pci_regs_behavior); + return -ENOMEM; + } ++ /* These bits are applicable only for PCI and reserved on PCIe */ ++ bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &= ++ ~GENMASK(15, 8); ++ bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &= ++ ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE | ++ PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT | ++ PCI_COMMAND_FAST_BACK) | ++ (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | ++ PCI_STATUS_DEVSEL_MASK) << 16); ++ bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &= ++ ~GENMASK(31, 24); ++ bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &= ++ ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK | ++ PCI_STATUS_DEVSEL_MASK) << 16); ++ bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &= ++ ~((PCI_BRIDGE_CTL_MASTER_ABORT | ++ BIT(8) | BIT(9) | BIT(11)) << 16); ++ bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &= ++ ~((PCI_BRIDGE_CTL_FAST_BACK) << 16); ++ bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &= ++ ~(BIT(10) << 16); + } + + if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) { diff --git a/queue-5.4/pci-pci-bridge-emul-set-pci_status_cap_list-for-pcie-device.patch b/queue-5.4/pci-pci-bridge-emul-set-pci_status_cap_list-for-pcie-device.patch new file mode 100644 index 00000000000..615e3a18029 --- /dev/null +++ b/queue-5.4/pci-pci-bridge-emul-set-pci_status_cap_list-for-pcie-device.patch @@ -0,0 +1,38 @@ +From 3be9d243b21724d49b65043d4520d688b6040b36 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +Date: Wed, 24 Nov 2021 16:59:44 +0100 +Subject: PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Pali Rohár + +commit 3be9d243b21724d49b65043d4520d688b6040b36 upstream. + +Since all PCI Express device Functions are required to implement the PCI +Express Capability structure, Capabilities List bit in PCI Status Register +must be hardwired to 1b. Capabilities Pointer register (which is already +set by pci-bride-emul.c driver) is valid only when Capabilities List is set +to 1b. + +Link: https://lore.kernel.org/r/20211124155944.1290-7-pali@kernel.org +Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic") +Signed-off-by: Pali Rohár +Signed-off-by: Lorenzo Pieralisi +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/pci-bridge-emul.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/pci/pci-bridge-emul.c ++++ b/drivers/pci/pci-bridge-emul.c +@@ -287,6 +287,7 @@ int pci_bridge_emul_init(struct pci_brid + + if (bridge->has_pcie) { + bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START; ++ bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST); + bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP; + bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4); + bridge->pcie_cap_regs_behavior = diff --git a/queue-5.4/pci-pciehp-fix-infinite-loop-in-irq-handler-upon-power-fault.patch b/queue-5.4/pci-pciehp-fix-infinite-loop-in-irq-handler-upon-power-fault.patch new file mode 100644 index 00000000000..8a24039f343 --- /dev/null +++ b/queue-5.4/pci-pciehp-fix-infinite-loop-in-irq-handler-upon-power-fault.patch @@ -0,0 +1,76 @@ +From 23584c1ed3e15a6f4bfab8dc5a88d94ab929ee12 Mon Sep 17 00:00:00 2001 +From: Lukas Wunner +Date: Wed, 17 Nov 2021 23:22:09 +0100 +Subject: PCI: pciehp: Fix infinite loop in IRQ handler upon power fault + +From: Lukas Wunner + +commit 23584c1ed3e15a6f4bfab8dc5a88d94ab929ee12 upstream. + +The Power Fault Detected bit in the Slot Status register differs from +all other hotplug events in that it is sticky: It can only be cleared +after turning off slot power. Per PCIe r5.0, sec. 6.7.1.8: + + If a power controller detects a main power fault on the hot-plug slot, + it must automatically set its internal main power fault latch [...]. + The main power fault latch is cleared when software turns off power to + the hot-plug slot. + +The stickiness used to cause interrupt storms and infinite loops which +were fixed in 2009 by commits 5651c48cfafe ("PCI pciehp: fix power fault +interrupt storm problem") and 99f0169c17f3 ("PCI: pciehp: enable +software notification on empty slots"). + +Unfortunately in 2020 the infinite loop issue was inadvertently +reintroduced by commit 8edf5332c393 ("PCI: pciehp: Fix MSI interrupt +race"): The hardirq handler pciehp_isr() clears the PFD bit until +pciehp's power_fault_detected flag is set. That happens in the IRQ +thread pciehp_ist(), which never learns of the event because the hardirq +handler is stuck in an infinite loop. Fix by setting the +power_fault_detected flag already in the hardirq handler. + +Link: https://bugzilla.kernel.org/show_bug.cgi?id=214989 +Link: https://lore.kernel.org/linux-pci/DM8PR11MB5702255A6A92F735D90A4446868B9@DM8PR11MB5702.namprd11.prod.outlook.com +Fixes: 8edf5332c393 ("PCI: pciehp: Fix MSI interrupt race") +Link: https://lore.kernel.org/r/66eaeef31d4997ceea357ad93259f290ededecfd.1637187226.git.lukas@wunner.de +Reported-by: Joseph Bao +Tested-by: Joseph Bao +Signed-off-by: Lukas Wunner +Signed-off-by: Bjorn Helgaas +Cc: stable@vger.kernel.org # v4.19+ +Cc: Stuart Hayes +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/hotplug/pciehp_hpc.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/pci/hotplug/pciehp_hpc.c ++++ b/drivers/pci/hotplug/pciehp_hpc.c +@@ -577,6 +577,8 @@ read_status: + */ + if (ctrl->power_fault_detected) + status &= ~PCI_EXP_SLTSTA_PFD; ++ else if (status & PCI_EXP_SLTSTA_PFD) ++ ctrl->power_fault_detected = true; + + events |= status; + if (!events) { +@@ -586,7 +588,7 @@ read_status: + } + + if (status) { +- pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events); ++ pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status); + + /* + * In MSI mode, all event bits must be zero before the port +@@ -660,8 +662,7 @@ static irqreturn_t pciehp_ist(int irq, v + } + + /* Check Power Fault Detected */ +- if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { +- ctrl->power_fault_detected = 1; ++ if (events & PCI_EXP_SLTSTA_PFD) { + ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl)); + pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, + PCI_EXP_SLTCTL_ATTN_IND_ON); diff --git a/queue-5.4/series b/queue-5.4/series index 557e049978b..84a5ef7e4fd 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -257,3 +257,8 @@ drm-etnaviv-limit-submit-sizes.patch drm-nouveau-kms-nv04-use-vzalloc-for-nv04_display.patch drm-bridge-analogix_dp-make-psr-exit-block-less.patch parisc-fix-lpa-and-lpa_user-defines.patch +pci-pciehp-fix-infinite-loop-in-irq-handler-upon-power-fault.patch +pci-pci-bridge-emul-properly-mark-reserved-pcie-bits-in-pci-config-space.patch +pci-pci-bridge-emul-correctly-set-pcie-capabilities.patch +pci-pci-bridge-emul-set-pci_status_cap_list-for-pcie-device.patch +xfrm-fix-policy-lookup-for-ipv6-gre-packets.patch diff --git a/queue-5.4/xfrm-fix-policy-lookup-for-ipv6-gre-packets.patch b/queue-5.4/xfrm-fix-policy-lookup-for-ipv6-gre-packets.patch new file mode 100644 index 00000000000..f1f2c5d2f67 --- /dev/null +++ b/queue-5.4/xfrm-fix-policy-lookup-for-ipv6-gre-packets.patch @@ -0,0 +1,100 @@ +From bcf141b2eb551b3477b24997ebc09c65f117a803 Mon Sep 17 00:00:00 2001 +From: Ghalem Boudour +Date: Fri, 19 Nov 2021 18:20:16 +0100 +Subject: xfrm: fix policy lookup for ipv6 gre packets + +From: Ghalem Boudour + +commit bcf141b2eb551b3477b24997ebc09c65f117a803 upstream. + +On egress side, xfrm lookup is called from __gre6_xmit() with the +fl6_gre_key field not initialized leading to policies selectors check +failure. Consequently, gre packets are sent without encryption. + +On ingress side, INET6_PROTO_NOPOLICY was set, thus packets were not +checked against xfrm policies. Like for egress side, fl6_gre_key should be +correctly set, this is now done in decode_session6(). + +Fixes: c12b395a4664 ("gre: Support GRE over IPv6") +Cc: stable@vger.kernel.org +Signed-off-by: Ghalem Boudour +Signed-off-by: Nicolas Dichtel +Signed-off-by: Steffen Klassert +Signed-off-by: Greg Kroah-Hartman +--- + net/ipv6/ip6_gre.c | 5 ++++- + net/xfrm/xfrm_policy.c | 21 +++++++++++++++++++++ + 2 files changed, 25 insertions(+), 1 deletion(-) + +--- a/net/ipv6/ip6_gre.c ++++ b/net/ipv6/ip6_gre.c +@@ -743,6 +743,7 @@ static netdev_tx_t __gre6_xmit(struct sk + fl6->daddr = key->u.ipv6.dst; + fl6->flowlabel = key->label; + fl6->flowi6_uid = sock_net_uid(dev_net(dev), NULL); ++ fl6->fl6_gre_key = tunnel_id_to_key32(key->tun_id); + + dsfield = key->tos; + flags = key->tun_flags & +@@ -978,6 +979,7 @@ static netdev_tx_t ip6erspan_tunnel_xmit + fl6.daddr = key->u.ipv6.dst; + fl6.flowlabel = key->label; + fl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL); ++ fl6.fl6_gre_key = tunnel_id_to_key32(key->tun_id); + + dsfield = key->tos; + if (!(tun_info->key.tun_flags & TUNNEL_ERSPAN_OPT)) +@@ -1085,6 +1087,7 @@ static void ip6gre_tnl_link_config_commo + fl6->flowi6_oif = p->link; + fl6->flowlabel = 0; + fl6->flowi6_proto = IPPROTO_GRE; ++ fl6->fl6_gre_key = t->parms.o_key; + + if (!(p->flags&IP6_TNL_F_USE_ORIG_TCLASS)) + fl6->flowlabel |= IPV6_TCLASS_MASK & p->flowinfo; +@@ -1530,7 +1533,7 @@ static void ip6gre_fb_tunnel_init(struct + static struct inet6_protocol ip6gre_protocol __read_mostly = { + .handler = gre_rcv, + .err_handler = ip6gre_err, +- .flags = INET6_PROTO_NOPOLICY|INET6_PROTO_FINAL, ++ .flags = INET6_PROTO_FINAL, + }; + + static void ip6gre_destroy_tunnels(struct net *net, struct list_head *head) +--- a/net/xfrm/xfrm_policy.c ++++ b/net/xfrm/xfrm_policy.c +@@ -33,6 +33,7 @@ + #include + #include + #include ++#include + #if IS_ENABLED(CONFIG_IPV6_MIP6) + #include + #endif +@@ -3443,6 +3444,26 @@ decode_session6(struct sk_buff *skb, str + } + fl6->flowi6_proto = nexthdr; + return; ++ case IPPROTO_GRE: ++ if (!onlyproto && ++ (nh + offset + 12 < skb->data || ++ pskb_may_pull(skb, nh + offset + 12 - skb->data))) { ++ struct gre_base_hdr *gre_hdr; ++ __be32 *gre_key; ++ ++ nh = skb_network_header(skb); ++ gre_hdr = (struct gre_base_hdr *)(nh + offset); ++ gre_key = (__be32 *)(gre_hdr + 1); ++ ++ if (gre_hdr->flags & GRE_KEY) { ++ if (gre_hdr->flags & GRE_CSUM) ++ gre_key++; ++ fl6->fl6_gre_key = *gre_key; ++ } ++ } ++ fl6->flowi6_proto = nexthdr; ++ return; ++ + #if IS_ENABLED(CONFIG_IPV6_MIP6) + case IPPROTO_MH: + offset += ipv6_optlen(exthdr);