From: Greg Kroah-Hartman Date: Wed, 12 Sep 2018 09:02:14 +0000 (+0200) Subject: 4.18-stable patches X-Git-Tag: v4.4.156~27 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=674a0bde15153df4cc642dd76d4417057dc2d84d;p=thirdparty%2Fkernel%2Fstable-queue.git 4.18-stable patches added patches: drm-amd-display-check-if-clock-source-in-use-before-disabling.patch drm-amd-display-don-t-share-clk-source-between-dp-and-hdmi.patch drm-amd-display-fix-type-of-variable.patch drm-amd-display-pass-connector-id-when-executing-vbios-ct.patch drm-amd-display-report-non-dp-display-as-disconnected-without-edid.patch drm-amd-display-update-clk-for-various-hdmi-color-depths.patch drm-amd-display-use-requested-hdmi-aspect-ratio.patch drm-amd-powerplay-fixed-uninitialized-value.patch drm-amd-pp-convert-voltage-unit-in-mv-4-to-mv-on-cz-st.patch drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch drm-amdgpu-add-new-firmware-id-for-vcn.patch drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch drm-amdgpu-add-vcn-support-in-psp-driver.patch drm-amdgpu-fix-incorrect-use-of-drm_file-pid.patch drm-amdgpu-fix-incorrect-use-of-fcheck.patch drm-amdgpu-update-tmr-mc-address.patch drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch drm-edid-quirk-vive-pro-vr-headset-non-desktop.patch drm-i915-re-apply-perform-link-quality-check-unconditionally-during-long-pulse.patch drm-rockchip-lvds-add-missing-of_node_put.patch drm-rockchip-vop-fix-irq-disabled-after-vop-driver-probed.patch drm-rockchip-vop-split-out-core-clock-enablement-into-separate-functions.patch mm-respect-arch_dup_mmap-return-value.patch uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch --- diff --git a/queue-4.18/drm-amd-display-check-if-clock-source-in-use-before-disabling.patch b/queue-4.18/drm-amd-display-check-if-clock-source-in-use-before-disabling.patch new file mode 100644 index 00000000000..d39dd243b27 --- /dev/null +++ b/queue-4.18/drm-amd-display-check-if-clock-source-in-use-before-disabling.patch @@ -0,0 +1,137 @@ +From ad8960a6cb06c446d0a391ce095f6f28edf36aff Mon Sep 17 00:00:00 2001 +From: Mikita Lipski +Date: Thu, 2 Aug 2018 09:45:09 -0400 +Subject: drm/amd/display: Check if clock source in use before disabling + +From: Mikita Lipski + +commit ad8960a6cb06c446d0a391ce095f6f28edf36aff upstream. + +[why] +We are disabling clock source while other pipes are still using +it, because we don't verify the number of pipes that share it. + +[how] +- Adding a function in resources to return the number of pipes +sharing the clock source. +- Checking that no one is sharing the clock source before disabling + +Signed-off-by: Mikita Lipski +Reviewed-by: Harry Wentland +Acked-by: Leo Li +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 46 ++++++++---- + drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 - + drivers/gpu/drm/amd/display/dc/inc/resource.h | 5 + + 3 files changed, 40 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -268,24 +268,30 @@ bool resource_construct( + + return true; + } ++static int find_matching_clock_source( ++ const struct resource_pool *pool, ++ struct clock_source *clock_source) ++{ + ++ int i; ++ ++ for (i = 0; i < pool->clk_src_count; i++) { ++ if (pool->clock_sources[i] == clock_source) ++ return i; ++ } ++ return -1; ++} + + void resource_unreference_clock_source( + struct resource_context *res_ctx, + const struct resource_pool *pool, + struct clock_source *clock_source) + { +- int i; +- +- for (i = 0; i < pool->clk_src_count; i++) { +- if (pool->clock_sources[i] != clock_source) +- continue; ++ int i = find_matching_clock_source(pool, clock_source); + ++ if (i > -1) + res_ctx->clock_source_ref_count[i]--; + +- break; +- } +- + if (pool->dp_clock_source == clock_source) + res_ctx->dp_clock_source_ref_count--; + } +@@ -295,19 +301,31 @@ void resource_reference_clock_source( + const struct resource_pool *pool, + struct clock_source *clock_source) + { +- int i; +- for (i = 0; i < pool->clk_src_count; i++) { +- if (pool->clock_sources[i] != clock_source) +- continue; ++ int i = find_matching_clock_source(pool, clock_source); + ++ if (i > -1) + res_ctx->clock_source_ref_count[i]++; +- break; +- } + + if (pool->dp_clock_source == clock_source) + res_ctx->dp_clock_source_ref_count++; + } + ++int resource_get_clock_source_reference( ++ struct resource_context *res_ctx, ++ const struct resource_pool *pool, ++ struct clock_source *clock_source) ++{ ++ int i = find_matching_clock_source(pool, clock_source); ++ ++ if (i > -1) ++ return res_ctx->clock_source_ref_count[i]; ++ ++ if (pool->dp_clock_source == clock_source) ++ return res_ctx->dp_clock_source_ref_count; ++ ++ return -1; ++} ++ + bool resource_are_streams_timing_synchronizable( + struct dc_stream_state *stream1, + struct dc_stream_state *stream2) +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1939,7 +1939,9 @@ static void dce110_reset_hw_ctx_wrap( + pipe_ctx_old->plane_res.mi->funcs->free_mem_input( + pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); + +- if (old_clk) ++ if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, ++ dc->res_pool, ++ old_clk)) + old_clk->funcs->cs_power_down(old_clk); + + dc->hwss.disable_plane(dc, pipe_ctx_old); +--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h +@@ -102,6 +102,11 @@ void resource_reference_clock_source( + const struct resource_pool *pool, + struct clock_source *clock_source); + ++int resource_get_clock_source_reference( ++ struct resource_context *res_ctx, ++ const struct resource_pool *pool, ++ struct clock_source *clock_source); ++ + bool resource_are_streams_timing_synchronizable( + struct dc_stream_state *stream1, + struct dc_stream_state *stream2); diff --git a/queue-4.18/drm-amd-display-don-t-share-clk-source-between-dp-and-hdmi.patch b/queue-4.18/drm-amd-display-don-t-share-clk-source-between-dp-and-hdmi.patch new file mode 100644 index 00000000000..ece00d89dd8 --- /dev/null +++ b/queue-4.18/drm-amd-display-don-t-share-clk-source-between-dp-and-hdmi.patch @@ -0,0 +1,124 @@ +From 3e27e10e2ecee0d3a0083f8ae76354ac9c6ad15c Mon Sep 17 00:00:00 2001 +From: Mikita Lipski +Date: Thu, 12 Jul 2018 16:44:05 -0400 +Subject: drm/amd/display: Don't share clk source between DP and HDMI + +From: Mikita Lipski + +commit 3e27e10e2ecee0d3a0083f8ae76354ac9c6ad15c upstream. + +[why] +Prevent clock source sharing between HDMI and DP connectors. +DP shouldn't be sharing its ref clock with phy clock, +which caused an issue of older ASICS booting up with multiple +diplays plugged in. + +[how] +Add an extra check that would prevent HDMI and DP sharing clk. + +Signed-off-by: Mikita Lipski +Reviewed-by: Hersen Wu +Acked-by: Bhawanpreet Lakha +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 +++++++++++++++- + drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 2 - + drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 3 ++ + 4 files changed, 26 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +@@ -330,6 +330,9 @@ bool resource_are_streams_timing_synchro + != stream2->timing.pix_clk_khz) + return false; + ++ if (stream1->clamping.c_depth != stream2->clamping.c_depth) ++ return false; ++ + if (stream1->phy_pix_clk != stream2->phy_pix_clk + && (!dc_is_dp_signal(stream1->signal) + || !dc_is_dp_signal(stream2->signal))) +@@ -337,6 +340,20 @@ bool resource_are_streams_timing_synchro + + return true; + } ++static bool is_dp_and_hdmi_sharable( ++ struct dc_stream_state *stream1, ++ struct dc_stream_state *stream2) ++{ ++ if (stream1->ctx->dc->caps.disable_dp_clk_share) ++ return false; ++ ++ if (stream1->clamping.c_depth != COLOR_DEPTH_888 || ++ stream2->clamping.c_depth != COLOR_DEPTH_888) ++ return false; ++ ++ return true; ++ ++} + + static bool is_sharable_clk_src( + const struct pipe_ctx *pipe_with_clk_src, +@@ -348,7 +365,10 @@ static bool is_sharable_clk_src( + if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL) + return false; + +- if (dc_is_dp_signal(pipe_with_clk_src->stream->signal)) ++ if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) || ++ (dc_is_dp_signal(pipe->stream->signal) && ++ !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream, ++ pipe->stream))) + return false; + + if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal) +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -77,6 +77,7 @@ struct dc_caps { + bool dual_link_dvi; + bool post_blend_color_processing; + bool force_dp_tps4_for_cp2520; ++ bool disable_dp_clk_share; + }; + + struct dc_dcc_surface_param { +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +@@ -884,7 +884,7 @@ static bool construct( + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; + dc->caps.dual_link_dvi = true; +- ++ dc->caps.disable_dp_clk_share = true; + for (i = 0; i < pool->base.pipe_count; i++) { + pool->base.timing_generators[i] = + dce100_timing_generator_create( +--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +@@ -902,6 +902,7 @@ static bool dce80_construct( + } + + dc->caps.max_planes = pool->base.pipe_count; ++ dc->caps.disable_dp_clk_share = true; + + if (!resource_construct(num_virtual_links, dc, &pool->base, + &res_create_funcs)) +@@ -1087,6 +1088,7 @@ static bool dce81_construct( + } + + dc->caps.max_planes = pool->base.pipe_count; ++ dc->caps.disable_dp_clk_share = true; + + if (!resource_construct(num_virtual_links, dc, &pool->base, + &res_create_funcs)) +@@ -1268,6 +1270,7 @@ static bool dce83_construct( + } + + dc->caps.max_planes = pool->base.pipe_count; ++ dc->caps.disable_dp_clk_share = true; + + if (!resource_construct(num_virtual_links, dc, &pool->base, + &res_create_funcs)) diff --git a/queue-4.18/drm-amd-display-fix-type-of-variable.patch b/queue-4.18/drm-amd-display-fix-type-of-variable.patch new file mode 100644 index 00000000000..d4e68a186c1 --- /dev/null +++ b/queue-4.18/drm-amd-display-fix-type-of-variable.patch @@ -0,0 +1,39 @@ +From fe78627d430435d22316fe39f2012ece31bf23c2 Mon Sep 17 00:00:00 2001 +From: "Gustavo A. R. Silva" +Date: Fri, 15 Jun 2018 08:32:28 -0500 +Subject: drm/amd/display: fix type of variable + +From: Gustavo A. R. Silva + +commit fe78627d430435d22316fe39f2012ece31bf23c2 upstream. + +Currently, the maximum value that *counter* can reach is 255, and +code at line 150: while (counter < 1000) { implies a bigger value +could be expected. + +Fix this by changing the type of variable *counter* from uint8_t +to uint16_t. + +Addresses-Coverity-ID: 1470030 ("Operands don't affect result") +Fixes: 2b6199a1d1b7 ("drm/amd/display: replace msleep with udelay in fbc path") +Signed-off-by: Gustavo A. R. Silva +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +@@ -143,7 +143,7 @@ static void wait_for_fbc_state_changed( + struct dce110_compressor *cp110, + bool enabled) + { +- uint8_t counter = 0; ++ uint16_t counter = 0; + uint32_t addr = mmFBC_STATUS; + uint32_t value; + diff --git a/queue-4.18/drm-amd-display-pass-connector-id-when-executing-vbios-ct.patch b/queue-4.18/drm-amd-display-pass-connector-id-when-executing-vbios-ct.patch new file mode 100644 index 00000000000..40daed99abf --- /dev/null +++ b/queue-4.18/drm-amd-display-pass-connector-id-when-executing-vbios-ct.patch @@ -0,0 +1,48 @@ +From 433149130c31de3f63b17b4ce08b45dab208f7e8 Mon Sep 17 00:00:00 2001 +From: Mikita Lipski +Date: Tue, 17 Jul 2018 10:52:19 -0400 +Subject: drm/amd/display: Pass connector id when executing VBIOS CT + +From: Mikita Lipski + +commit 433149130c31de3f63b17b4ce08b45dab208f7e8 upstream. + +[why] +Older ASICs require both phys_id and connector_id +to execute bios command table. If we are not passing the +right connector_id - it can lead to a black screen. + +[how] +Set connector_obj_id when executing vbios command table + +Signed-off-by: Mikita Lipski +Reviewed-by: Hersen Wu +Acked-by: Leo Li +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +@@ -919,7 +919,7 @@ void dce110_link_encoder_enable_tmds_out + enum bp_result result; + + /* Enable the PHY */ +- ++ cntl.connector_obj_id = enc110->base.connector; + cntl.action = TRANSMITTER_CONTROL_ENABLE; + cntl.engine_id = enc->preferred_engine; + cntl.transmitter = enc110->base.transmitter; +@@ -961,7 +961,7 @@ void dce110_link_encoder_enable_dp_outpu + * We need to set number of lanes manually. + */ + configure_encoder(enc110, link_settings); +- ++ cntl.connector_obj_id = enc110->base.connector; + cntl.action = TRANSMITTER_CONTROL_ENABLE; + cntl.engine_id = enc->preferred_engine; + cntl.transmitter = enc110->base.transmitter; diff --git a/queue-4.18/drm-amd-display-report-non-dp-display-as-disconnected-without-edid.patch b/queue-4.18/drm-amd-display-report-non-dp-display-as-disconnected-without-edid.patch new file mode 100644 index 00000000000..884b13fbdd8 --- /dev/null +++ b/queue-4.18/drm-amd-display-report-non-dp-display-as-disconnected-without-edid.patch @@ -0,0 +1,54 @@ +From 01dc285d5cd89b77686d8baef8482c58d7dc3ead Mon Sep 17 00:00:00 2001 +From: Harry Wentland +Date: Wed, 1 Aug 2018 10:48:23 -0400 +Subject: drm/amd/display: Report non-DP display as disconnected without EDID + +From: Harry Wentland + +commit 01dc285d5cd89b77686d8baef8482c58d7dc3ead upstream. + +[Why] +Some boards seem to have a problem where HPD is high on HDMI even though +no display is connected. We don't want to report these as connected. DP +spec still requires us to report DP displays as connected when HPD is +high but we can't read the EDID in order to go to fail-safe mode. + +[How] +If connector_signal is not DP abort detection if we can't retrieve the +EDID. + +v2: Add Bugzilla and stable + +Bugzilla: https://bugs.freedesktop.org/107390 +Bugzilla: https://bugs.freedesktop.org/106846 +Cc: stable@vger.kernel.org +Signed-off-by: Harry Wentland +Acked-by: Alex Deucher +Reviewed-by: Nicholas Kazlauskas +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -728,6 +728,17 @@ bool dc_link_detect(struct dc_link *link + break; + case EDID_NO_RESPONSE: + DC_LOG_ERROR("No EDID read.\n"); ++ ++ /* ++ * Abort detection for non-DP connectors if we have ++ * no EDID ++ * ++ * DP needs to report as connected if HDP is high ++ * even if we have no EDID in order to go to ++ * fail-safe mode ++ */ ++ if (!dc_is_dp_signal(link->connector_signal)) ++ return false; + default: + break; + } diff --git a/queue-4.18/drm-amd-display-update-clk-for-various-hdmi-color-depths.patch b/queue-4.18/drm-amd-display-update-clk-for-various-hdmi-color-depths.patch new file mode 100644 index 00000000000..c4b7595c99b --- /dev/null +++ b/queue-4.18/drm-amd-display-update-clk-for-various-hdmi-color-depths.patch @@ -0,0 +1,57 @@ +From 81aca8e75c1b046865fb2badef95a0dcff6f73de Mon Sep 17 00:00:00 2001 +From: Mikita Lipski +Date: Fri, 13 Jul 2018 09:07:35 -0400 +Subject: drm/amd/display: update clk for various HDMI color depths + +From: Mikita Lipski + +commit 81aca8e75c1b046865fb2badef95a0dcff6f73de upstream. + +[why] +When programming tonga's connector's backend we didn't take +in account that HDMI's colour depth might be more than 8bpc +therefore we need to add a switch statement that would adjust +the pixel clock accordingly. + +[how] +Add a switch statement updating clock by its appropriate +coefficient. + +Signed-off-by: Mikita Lipski +Reviewed-by: Charlene Liu +Acked-by: Bhawanpreet Lakha +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/bios/command_table.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c +@@ -808,6 +808,24 @@ static enum bp_result transmitter_contro + * (=1: 8bpp, =1.25: 10bpp, =1.5:12bpp, =2: 16bpp) + * LVDS mode: usPixelClock = pixel clock + */ ++ if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A) { ++ switch (cntl->color_depth) { ++ case COLOR_DEPTH_101010: ++ params.usSymClock = ++ cpu_to_le16((le16_to_cpu(params.usSymClock) * 30) / 24); ++ break; ++ case COLOR_DEPTH_121212: ++ params.usSymClock = ++ cpu_to_le16((le16_to_cpu(params.usSymClock) * 36) / 24); ++ break; ++ case COLOR_DEPTH_161616: ++ params.usSymClock = ++ cpu_to_le16((le16_to_cpu(params.usSymClock) * 48) / 24); ++ break; ++ default: ++ break; ++ } ++ } + + if (EXEC_BIOS_CMD_TABLE(UNIPHYTransmitterControl, params)) + result = BP_RESULT_OK; diff --git a/queue-4.18/drm-amd-display-use-requested-hdmi-aspect-ratio.patch b/queue-4.18/drm-amd-display-use-requested-hdmi-aspect-ratio.patch new file mode 100644 index 00000000000..632bbdd9d9e --- /dev/null +++ b/queue-4.18/drm-amd-display-use-requested-hdmi-aspect-ratio.patch @@ -0,0 +1,48 @@ +From e11d41472a50742c16d53c968e143fb498fa482f Mon Sep 17 00:00:00 2001 +From: "Leo (Sunpeng) Li" +Date: Thu, 19 Jul 2018 08:22:16 -0400 +Subject: drm/amd/display: Use requested HDMI aspect ratio + +From: Leo (Sunpeng) Li + +commit e11d41472a50742c16d53c968e143fb498fa482f upstream. + +[Why] +The DRM mode's HDMI picture aspect ratio field was never saved in +dc_stream's timing struct. This causes us to mistake a new stream to +have the same timings as the old, even though the user has requested a +different aspect ratio. + +[How] +Save DRM's aspect ratio field within dc_stream's timing struct. + +Bug: https://bugs.freedesktop.org/show_bug.cgi?id=107153 +Signed-off-by: Leo (Sunpeng) Li +Reviewed-by: Mikita Lipski +Acked-by: Bhawanpreet Lakha +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++------- + 1 file changed, 2 insertions(+), 7 deletions(-) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -2124,13 +2124,8 @@ convert_color_depth_from_display_info(co + static enum dc_aspect_ratio + get_aspect_ratio(const struct drm_display_mode *mode_in) + { +- int32_t width = mode_in->crtc_hdisplay * 9; +- int32_t height = mode_in->crtc_vdisplay * 16; +- +- if ((width - height) < 10 && (width - height) > -10) +- return ASPECT_RATIO_16_9; +- else +- return ASPECT_RATIO_4_3; ++ /* 1-1 mapping, since both enums follow the HDMI spec. */ ++ return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; + } + + static enum dc_color_space diff --git a/queue-4.18/drm-amd-powerplay-fixed-uninitialized-value.patch b/queue-4.18/drm-amd-powerplay-fixed-uninitialized-value.patch new file mode 100644 index 00000000000..eac2c87d6bd --- /dev/null +++ b/queue-4.18/drm-amd-powerplay-fixed-uninitialized-value.patch @@ -0,0 +1,33 @@ +From 1ce0688f3f6a9e9d34ae66bf779d54855def7bec Mon Sep 17 00:00:00 2001 +From: Evan Quan +Date: Thu, 19 Jul 2018 13:21:43 +0800 +Subject: drm/amd/powerplay: fixed uninitialized value + +From: Evan Quan + +commit 1ce0688f3f6a9e9d34ae66bf779d54855def7bec upstream. + +The 'result' is not initialized correctly. It causes the API +return an error code even on success. + +Signed-off-by: Evan Quan +Acked-by: Huang Rui +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +@@ -490,7 +490,7 @@ static int vega12_get_number_dpm_level(s + static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, + PPCLK_e clkID, uint32_t index, uint32_t *clock) + { +- int result; ++ int result = 0; + + /* + *SMU expects the Clock ID to be in the top 16 bits. diff --git a/queue-4.18/drm-amd-pp-convert-voltage-unit-in-mv-4-to-mv-on-cz-st.patch b/queue-4.18/drm-amd-pp-convert-voltage-unit-in-mv-4-to-mv-on-cz-st.patch new file mode 100644 index 00000000000..2145d492afd --- /dev/null +++ b/queue-4.18/drm-amd-pp-convert-voltage-unit-in-mv-4-to-mv-on-cz-st.patch @@ -0,0 +1,48 @@ +From 8a50bb47a863c3cb8950a2e810448c9a82a9d446 Mon Sep 17 00:00:00 2001 +From: Rex Zhu +Date: Wed, 25 Jul 2018 11:45:03 +0800 +Subject: drm/amd/pp: Convert voltage unit in mV*4 to mV on CZ/ST + +From: Rex Zhu + +commit 8a50bb47a863c3cb8950a2e810448c9a82a9d446 upstream. + +the voltage showed in debugfs and hwmon should be in mV + +Reviewed-by: Evan Quan +Acked-by: Alex Deucher +Signed-off-by: Rex Zhu +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +@@ -244,6 +244,7 @@ static int smu8_initialize_dpm_defaults( + return 0; + } + ++/* convert form 8bit vid to real voltage in mV*4 */ + static uint32_t smu8_convert_8Bit_index_to_voltage( + struct pp_hwmgr *hwmgr, uint16_t voltage) + { +@@ -1702,13 +1703,13 @@ static int smu8_read_sensor(struct pp_hw + case AMDGPU_PP_SENSOR_VDDNB: + tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) & + CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT; +- vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp); ++ vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp) / 4; + *((uint32_t *)value) = vddnb; + return 0; + case AMDGPU_PP_SENSOR_VDDGFX: + tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) & + CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT; +- vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp); ++ vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp) / 4; + *((uint32_t *)value) = vddgfx; + return 0; + case AMDGPU_PP_SENSOR_UVD_VCLK: diff --git a/queue-4.18/drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch b/queue-4.18/drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch new file mode 100644 index 00000000000..edc548ba75b --- /dev/null +++ b/queue-4.18/drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch @@ -0,0 +1,75 @@ +From 2d227ec2c11c568910299e8f913bac2dda47397c Mon Sep 17 00:00:00 2001 +From: Rex Zhu +Date: Fri, 20 Jul 2018 16:26:46 +0800 +Subject: drm/amd/pp/Polaris12: Fix a chunk of registers missed to program + +From: Rex Zhu + +commit 2d227ec2c11c568910299e8f913bac2dda47397c upstream. + +DIDTConfig_Polaris12[] table missed a big chunk of data. + +Pointed by aidan.fabius + +Reviewed-by: Alex Deucher +Signed-off-by: Rex Zhu +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c | 43 +++++++++++++++++++ + 1 file changed, 43 insertions(+) + +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c +@@ -403,6 +403,49 @@ static const struct gpu_pt_config_reg DI + { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, + + { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL_OCP, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_0_MASK, DIDT_SQ_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x005a, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_1_MASK, DIDT_SQ_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__UNUSED_2_MASK, DIDT_SQ_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT, 0x0ebb, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0001, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__UNUSED_0_MASK, DIDT_SQ_CTRL0__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT, 0x000a, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT, 0x0010, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT, 0x0017, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT0_3, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT, 0x002f, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT, 0x0046, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT, 0x005d, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_WEIGHT4_7, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, ++ { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff, GPU_CONFIGREG_DIDT_IND }, ++ ++ { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__UNUSED_0_MASK, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND }, + { ixDIDT_TD_CTRL_OCP, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT, 0x00ff, GPU_CONFIGREG_DIDT_IND }, + + { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND }, diff --git a/queue-4.18/drm-amdgpu-add-new-firmware-id-for-vcn.patch b/queue-4.18/drm-amdgpu-add-new-firmware-id-for-vcn.patch new file mode 100644 index 00000000000..a5e8d543ea5 --- /dev/null +++ b/queue-4.18/drm-amdgpu-add-new-firmware-id-for-vcn.patch @@ -0,0 +1,34 @@ +From c9ca989696ff28ffb015cc2b7c5577938ef2626c Mon Sep 17 00:00:00 2001 +From: Likun Gao +Date: Fri, 10 Aug 2018 00:31:40 +0800 +Subject: drm/amdgpu:add new firmware id for VCN + +From: Likun Gao + +commit c9ca989696ff28ffb015cc2b7c5577938ef2626c upstream. + +Add the new firmware id for VCN into the enum + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +@@ -194,6 +194,7 @@ enum AMDGPU_UCODE_ID { + AMDGPU_UCODE_ID_SMC, + AMDGPU_UCODE_ID_UVD, + AMDGPU_UCODE_ID_VCE, ++ AMDGPU_UCODE_ID_VCN, + AMDGPU_UCODE_ID_MAXIMUM, + }; + diff --git a/queue-4.18/drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch b/queue-4.18/drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch new file mode 100644 index 00000000000..f84b2c939b1 --- /dev/null +++ b/queue-4.18/drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch @@ -0,0 +1,37 @@ +From abf412b3efb2f943d9b98a489e9aca836be21333 Mon Sep 17 00:00:00 2001 +From: James Zhu +Date: Fri, 10 Aug 2018 00:31:38 +0800 +Subject: drm/amdgpu:add tmr mc address into amdgpu_firmware_info + +From: James Zhu + +commit abf412b3efb2f943d9b98a489e9aca836be21333 upstream. + +amdgpu IP blocks booting need Trust Memory Region(tmr) mc address +of its firmware which is loaded by PSP + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +@@ -226,6 +226,9 @@ struct amdgpu_firmware_info { + void *kaddr; + /* ucode_size_bytes */ + uint32_t ucode_size; ++ /* starting tmr mc address */ ++ uint32_t tmr_mc_addr_lo; ++ uint32_t tmr_mc_addr_hi; + }; + + void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); diff --git a/queue-4.18/drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch b/queue-4.18/drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch new file mode 100644 index 00000000000..22c1191054e --- /dev/null +++ b/queue-4.18/drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch @@ -0,0 +1,126 @@ +From 4d77c0f676e910fb1f1870738aa4bd168f253621 Mon Sep 17 00:00:00 2001 +From: Likun Gao +Date: Fri, 10 Aug 2018 00:31:42 +0800 +Subject: drm/amdgpu:add VCN booting with firmware loaded by PSP + +From: Likun Gao + +commit 4d77c0f676e910fb1f1870738aa4bd168f253621 upstream. + +Setup psp firmware loading for VCN, and make VCN block +booting from tmr mac address. + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 ++++++++------ + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 38 +++++++++++++++++++++++++------- + 2 files changed, 40 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +@@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_dev + version_major, version_minor, family_id); + } + +- bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) +- + AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE ++ bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE + + AMDGPU_VCN_SESSION_SIZE * 40; ++ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ++ bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); + r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo, + &adev->vcn.gpu_addr, &adev->vcn.cpu_addr); +@@ -187,11 +188,13 @@ int amdgpu_vcn_resume(struct amdgpu_devi + unsigned offset; + + hdr = (const struct common_firmware_header *)adev->vcn.fw->data; +- offset = le32_to_cpu(hdr->ucode_array_offset_bytes); +- memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset, +- le32_to_cpu(hdr->ucode_size_bytes)); +- size -= le32_to_cpu(hdr->ucode_size_bytes); +- ptr += le32_to_cpu(hdr->ucode_size_bytes); ++ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { ++ offset = le32_to_cpu(hdr->ucode_array_offset_bytes); ++ memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data + offset, ++ le32_to_cpu(hdr->ucode_size_bytes)); ++ size -= le32_to_cpu(hdr->ucode_size_bytes); ++ ptr += le32_to_cpu(hdr->ucode_size_bytes); ++ } + memset_io(ptr, 0, size); + } + +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -90,6 +90,16 @@ static int vcn_v1_0_sw_init(void *handle + if (r) + return r; + ++ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { ++ const struct common_firmware_header *hdr; ++ hdr = (const struct common_firmware_header *)adev->vcn.fw->data; ++ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; ++ adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; ++ adev->firmware.fw_size += ++ ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); ++ DRM_INFO("PSP loading VCN firmware\n"); ++ } ++ + r = amdgpu_vcn_resume(adev); + if (r) + return r; +@@ -241,26 +251,38 @@ static int vcn_v1_0_resume(void *handle) + static void vcn_v1_0_mc_resume(struct amdgpu_device *adev) + { + uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); ++ uint32_t offset; + +- WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, ++ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { ++ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, ++ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); ++ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, ++ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); ++ WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); ++ offset = 0; ++ } else { ++ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.gpu_addr)); +- WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, ++ WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.gpu_addr)); +- WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, +- AMDGPU_UVD_FIRMWARE_OFFSET >> 3); ++ offset = size; ++ WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, ++ AMDGPU_UVD_FIRMWARE_OFFSET >> 3); ++ } ++ + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); + + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, +- lower_32_bits(adev->vcn.gpu_addr + size)); ++ lower_32_bits(adev->vcn.gpu_addr + offset)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, +- upper_32_bits(adev->vcn.gpu_addr + size)); ++ upper_32_bits(adev->vcn.gpu_addr + offset)); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_HEAP_SIZE); + + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, +- lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); ++ lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); + WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, +- upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE)); ++ upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE)); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); + WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, + AMDGPU_VCN_STACK_SIZE + (AMDGPU_VCN_SESSION_SIZE * 40)); diff --git a/queue-4.18/drm-amdgpu-add-vcn-support-in-psp-driver.patch b/queue-4.18/drm-amdgpu-add-vcn-support-in-psp-driver.patch new file mode 100644 index 00000000000..284a803ea9b --- /dev/null +++ b/queue-4.18/drm-amdgpu-add-vcn-support-in-psp-driver.patch @@ -0,0 +1,36 @@ +From 235ac9de625a0a586093ad81b3de6f7d7ab913ed Mon Sep 17 00:00:00 2001 +From: Likun Gao +Date: Fri, 10 Aug 2018 00:31:41 +0800 +Subject: drm/amdgpu:add VCN support in PSP driver + +From: Likun Gao + +commit 235ac9de625a0a586093ad81b3de6f7d7ab913ed upstream. + +Add VCN support in PSP driver + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +@@ -88,6 +88,9 @@ psp_v10_0_get_fw_type(struct amdgpu_firm + case AMDGPU_UCODE_ID_VCE: + *type = GFX_FW_TYPE_VCE; + break; ++ case AMDGPU_UCODE_ID_VCN: ++ *type = GFX_FW_TYPE_VCN; ++ break; + case AMDGPU_UCODE_ID_MAXIMUM: + default: + return -EINVAL; diff --git a/queue-4.18/drm-amdgpu-fix-incorrect-use-of-drm_file-pid.patch b/queue-4.18/drm-amdgpu-fix-incorrect-use-of-drm_file-pid.patch new file mode 100644 index 00000000000..d975f17db4d --- /dev/null +++ b/queue-4.18/drm-amdgpu-fix-incorrect-use-of-drm_file-pid.patch @@ -0,0 +1,60 @@ +From c4aed87630d41ee54e2ee23d4583c3dd423296dd Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Fri, 17 Aug 2018 19:38:33 +0200 +Subject: drm/amdgpu: fix incorrect use of drm_file->pid +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit c4aed87630d41ee54e2ee23d4583c3dd423296dd upstream. + +That's the PID of the creator of the file (usually the X server) and not +the end user of the file. + +Signed-off-by: Christian König +Acked-by: Alex Deucher +Signed-off-by: Alex Deucher +CC: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 19 ++++--------------- + 1 file changed, 4 insertions(+), 15 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +@@ -55,7 +55,6 @@ static int amdgpu_sched_process_priority + { + struct file *filp = fget(fd); + struct drm_file *file; +- struct pid *pid; + struct amdgpu_fpriv *fpriv; + struct amdgpu_ctx *ctx; + uint32_t id; +@@ -63,20 +62,10 @@ static int amdgpu_sched_process_priority + if (!filp) + return -EINVAL; + +- pid = get_pid(((struct drm_file *)filp->private_data)->pid); +- +- mutex_lock(&adev->ddev->filelist_mutex); +- list_for_each_entry(file, &adev->ddev->filelist, lhead) { +- if (file->pid != pid) +- continue; +- +- fpriv = file->driver_priv; +- idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id) +- amdgpu_ctx_priority_override(ctx, priority); +- } +- mutex_unlock(&adev->ddev->filelist_mutex); +- +- put_pid(pid); ++ file = filp->private_data; ++ fpriv = file->driver_priv; ++ idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id) ++ amdgpu_ctx_priority_override(ctx, priority); + + fput(filp); + diff --git a/queue-4.18/drm-amdgpu-fix-incorrect-use-of-fcheck.patch b/queue-4.18/drm-amdgpu-fix-incorrect-use-of-fcheck.patch new file mode 100644 index 00000000000..4e2d998a33a --- /dev/null +++ b/queue-4.18/drm-amdgpu-fix-incorrect-use-of-fcheck.patch @@ -0,0 +1,44 @@ +From bce31d4c1ae8865d6382e3a27b07b4bb8e020ade Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= +Date: Fri, 17 Aug 2018 19:36:08 +0200 +Subject: drm/amdgpu: fix incorrect use of fcheck +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Christian König + +commit bce31d4c1ae8865d6382e3a27b07b4bb8e020ade upstream. + +The usage isn't RCU protected. + +Signed-off-by: Christian König +Acked-by: Alex Deucher +Signed-off-by: Alex Deucher +CC: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +@@ -53,7 +53,7 @@ static int amdgpu_sched_process_priority + int fd, + enum drm_sched_priority priority) + { +- struct file *filp = fcheck(fd); ++ struct file *filp = fget(fd); + struct drm_file *file; + struct pid *pid; + struct amdgpu_fpriv *fpriv; +@@ -78,6 +78,8 @@ static int amdgpu_sched_process_priority + + put_pid(pid); + ++ fput(filp); ++ + return 0; + } + diff --git a/queue-4.18/drm-amdgpu-update-tmr-mc-address.patch b/queue-4.18/drm-amdgpu-update-tmr-mc-address.patch new file mode 100644 index 00000000000..49991661b7d --- /dev/null +++ b/queue-4.18/drm-amdgpu-update-tmr-mc-address.patch @@ -0,0 +1,39 @@ +From 435198f33b56d7b875a8173a0227ddf0de285aa1 Mon Sep 17 00:00:00 2001 +From: James Zhu +Date: Fri, 10 Aug 2018 00:31:39 +0800 +Subject: drm/amdgpu: update tmr mc address + +From: James Zhu + +commit 435198f33b56d7b875a8173a0227ddf0de285aa1 upstream. + +Update tmr mc address with firmware loading address +which is returned from PSP firmware + +Signed-off-by: James Zhu +Reviewed-by: Alex Deucher +Acked-by: Huang Rui +Reviewed-by: Likun Gao +Signed-off-by: Likun Gao +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +@@ -131,6 +131,11 @@ psp_cmd_submit_buf(struct psp_context *p + msleep(1); + } + ++ if (ucode) { ++ ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; ++ ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; ++ } ++ + return ret; + } + diff --git a/queue-4.18/drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch b/queue-4.18/drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch new file mode 100644 index 00000000000..8ace994dc8d --- /dev/null +++ b/queue-4.18/drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch @@ -0,0 +1,37 @@ +From 25da75043f8690fd083878447c91f289dfb63b87 Mon Sep 17 00:00:00 2001 +From: Kai-Heng Feng +Date: Thu, 23 Aug 2018 05:53:32 +0000 +Subject: drm/edid: Add 6 bpc quirk for SDC panel in Lenovo B50-80 + +From: Kai-Heng Feng + +commit 25da75043f8690fd083878447c91f289dfb63b87 upstream. + +Another panel that reports "DFP 1.x compliant TMDS" but it supports 6bpc +instead of 8 bpc. + +Apply 6 bpc quirk for the panel to fix it. + +BugLink: https://bugs.launchpad.net/bugs/1788308 +Cc: # v4.8+ +Signed-off-by: Kai-Heng Feng +Signed-off-by: Daniel Vetter +Link: https://patchwork.freedesktop.org/patch/msgid/20180823055332.7723-1-kai.heng.feng@canonical.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_edid.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -116,6 +116,9 @@ static const struct edid_quirk { + /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ + { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, + ++ /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ ++ { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, ++ + /* Belinea 10 15 55 */ + { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, + { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, diff --git a/queue-4.18/drm-edid-quirk-vive-pro-vr-headset-non-desktop.patch b/queue-4.18/drm-edid-quirk-vive-pro-vr-headset-non-desktop.patch new file mode 100644 index 00000000000..f21ab101068 --- /dev/null +++ b/queue-4.18/drm-edid-quirk-vive-pro-vr-headset-non-desktop.patch @@ -0,0 +1,36 @@ +From 6931317c714885f2d792e8150ef6715d416ac681 Mon Sep 17 00:00:00 2001 +From: Lubosz Sarnecki +Date: Tue, 29 May 2018 13:52:15 +0200 +Subject: drm/edid: Quirk Vive Pro VR headset non-desktop. + +From: Lubosz Sarnecki + +commit 6931317c714885f2d792e8150ef6715d416ac681 upstream. + +This adds the Vive Pro's EDID information and +sets EDID_QUIRK_NON_DESKTOP. + +Signed-off-by: Lubosz Sarnecki +Signed-off-by: Daniel Stone +Reviewed-by: Daniel Stone +Cc: # v4.15+ +Link: https://patchwork.freedesktop.org/patch/msgid/20180529115215.4526-1-lubosz.sarnecki@collabora.com +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/drm_edid.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -163,8 +163,9 @@ static const struct edid_quirk { + /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ + { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, + +- /* HTC Vive VR Headset */ ++ /* HTC Vive and Vive Pro VR Headsets */ + { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, ++ { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, + + /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ + { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, diff --git a/queue-4.18/drm-i915-re-apply-perform-link-quality-check-unconditionally-during-long-pulse.patch b/queue-4.18/drm-i915-re-apply-perform-link-quality-check-unconditionally-during-long-pulse.patch new file mode 100644 index 00000000000..11a809d1f38 --- /dev/null +++ b/queue-4.18/drm-i915-re-apply-perform-link-quality-check-unconditionally-during-long-pulse.patch @@ -0,0 +1,95 @@ +From 399334708b4f07b107094e5db4a390f0f25d2d4f Mon Sep 17 00:00:00 2001 +From: Jan-Marek Glogowski +Date: Sat, 25 Aug 2018 15:10:35 -0400 +Subject: drm/i915: Re-apply "Perform link quality check, unconditionally during long pulse" + +From: Jan-Marek Glogowski + +commit 399334708b4f07b107094e5db4a390f0f25d2d4f upstream. + +This re-applies the workaround for "some DP sinks, [which] are a +little nuts" from commit 1a36147bb939 ("drm/i915: Perform link +quality check unconditionally during long pulse"). +It makes the secondary AOC E2460P monitor connected via DP to an +acer Veriton N4640G usable again. + +This hunk was dropped in commit c85d200e8321 ("drm/i915: Move SST +DP link retraining into the ->post_hotplug() hook") + +Fixes: c85d200e8321 ("drm/i915: Move SST DP link retraining into the ->post_hotplug() hook") +[Cleaned up commit message, added stable cc] +Signed-off-by: Lyude Paul +Signed-off-by: Jan-Marek Glogowski +Cc: stable@vger.kernel.org +Link: https://patchwork.freedesktop.org/patch/msgid/20180825191035.3945-1-lyude@redhat.com +(cherry picked from commit 3cf71bc9904d7ee4a25a822c5dcb54c7804ea388) +Signed-off-by: Rodrigo Vivi +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_dp.c | 33 +++++++++++++++++++-------------- + 1 file changed, 19 insertions(+), 14 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_dp.c ++++ b/drivers/gpu/drm/i915/intel_dp.c +@@ -4293,18 +4293,6 @@ intel_dp_needs_link_retrain(struct intel + return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); + } + +-/* +- * If display is now connected check links status, +- * there has been known issues of link loss triggering +- * long pulse. +- * +- * Some sinks (eg. ASUS PB287Q) seem to perform some +- * weird HPD ping pong during modesets. So we can apparently +- * end up with HPD going low during a modeset, and then +- * going back up soon after. And once that happens we must +- * retrain the link to get a picture. That's in case no +- * userspace component reacted to intermittent HPD dip. +- */ + int intel_dp_retrain_link(struct intel_encoder *encoder, + struct drm_modeset_acquire_ctx *ctx) + { +@@ -4794,7 +4782,8 @@ intel_dp_unset_edid(struct intel_dp *int + } + + static int +-intel_dp_long_pulse(struct intel_connector *connector) ++intel_dp_long_pulse(struct intel_connector *connector, ++ struct drm_modeset_acquire_ctx *ctx) + { + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_attached_dp(&connector->base); +@@ -4853,6 +4842,22 @@ intel_dp_long_pulse(struct intel_connect + */ + status = connector_status_disconnected; + goto out; ++ } else { ++ /* ++ * If display is now connected check links status, ++ * there has been known issues of link loss triggering ++ * long pulse. ++ * ++ * Some sinks (eg. ASUS PB287Q) seem to perform some ++ * weird HPD ping pong during modesets. So we can apparently ++ * end up with HPD going low during a modeset, and then ++ * going back up soon after. And once that happens we must ++ * retrain the link to get a picture. That's in case no ++ * userspace component reacted to intermittent HPD dip. ++ */ ++ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; ++ ++ intel_dp_retrain_link(encoder, ctx); + } + + /* +@@ -4914,7 +4919,7 @@ intel_dp_detect(struct drm_connector *co + return ret; + } + +- status = intel_dp_long_pulse(intel_dp->attached_connector); ++ status = intel_dp_long_pulse(intel_dp->attached_connector, ctx); + } + + intel_dp->detect_done = false; diff --git a/queue-4.18/drm-rockchip-lvds-add-missing-of_node_put.patch b/queue-4.18/drm-rockchip-lvds-add-missing-of_node_put.patch new file mode 100644 index 00000000000..e5867ea970f --- /dev/null +++ b/queue-4.18/drm-rockchip-lvds-add-missing-of_node_put.patch @@ -0,0 +1,57 @@ +From ebfb081edc8afd250a6d290c37481bfb2262e7cb Mon Sep 17 00:00:00 2001 +From: Julia Lawall +Date: Wed, 23 May 2018 21:07:16 +0200 +Subject: drm/rockchip: lvds: add missing of_node_put + +From: Julia Lawall + +commit ebfb081edc8afd250a6d290c37481bfb2262e7cb upstream. + +The device node iterators perform an of_node_get on each iteration, so a +jump out of the loop requires an of_node_put. + +The semantic patch that fixes this problem is as follows +(http://coccinelle.lip6.fr): + +// +@@ +expression root,e; +local idexpression child; +iterator name for_each_child_of_node; +@@ + + for_each_child_of_node(root, child) { + ... when != of_node_put(child) + when != e = child ++ of_node_put(child); +? break; + ... +} +... when != child +// + +Fixes: 34cc0aa25456 ("drm/rockchip: Add support for Rockchip Soc LVDS") +Cc: stable@vger.kernel.org +Signed-off-by: Julia Lawall +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/1527102436-13447-6-git-send-email-Julia.Lawall@lip6.fr +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/rockchip/rockchip_lvds.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c ++++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c +@@ -363,8 +363,10 @@ static int rockchip_lvds_bind(struct dev + of_property_read_u32(endpoint, "reg", &endpoint_id); + ret = drm_of_find_panel_or_bridge(dev->of_node, 1, endpoint_id, + &lvds->panel, &lvds->bridge); +- if (!ret) ++ if (!ret) { ++ of_node_put(endpoint); + break; ++ } + } + if (!child_count) { + DRM_DEV_ERROR(dev, "lvds port does not have any children\n"); diff --git a/queue-4.18/drm-rockchip-vop-fix-irq-disabled-after-vop-driver-probed.patch b/queue-4.18/drm-rockchip-vop-fix-irq-disabled-after-vop-driver-probed.patch new file mode 100644 index 00000000000..f5c8d7e69af --- /dev/null +++ b/queue-4.18/drm-rockchip-vop-fix-irq-disabled-after-vop-driver-probed.patch @@ -0,0 +1,113 @@ +From 6456314ff1de246414a43e3132075b70b3e050ac Mon Sep 17 00:00:00 2001 +From: Sandy Huang +Date: Tue, 12 Jun 2018 15:20:28 +0200 +Subject: drm/rockchip: vop: fix irq disabled after vop driver probed + +From: Sandy Huang + +commit 6456314ff1de246414a43e3132075b70b3e050ac upstream. + +The vop irq is shared between vop and iommu and irq probing in the +iommu driver moved to the probe function recently. This can in some +cases lead to a stall if the irq is triggered while the vop driver +still has it disabled, but the vop irq handler gets called. + +But there is no real need to disable the irq, as the vop can simply +also track its enabled state and ignore irqs in that case. +For this we can simply check the power-domain state of the vop, +similar to how the iommu driver does it. + +So remove the enable/disable handling and add appropriate condition +to the irq handler. + +changes in v2: +- move to just check the power-domain state +- add clock handling +changes in v3: +- clarify comment to speak of runtime-pm not power-domain +changes in v4: +- address Marc's comments (clk-enable WARN_ON and style improvement) + +Fixes: d0b912bd4c23 ("iommu/rockchip: Request irqs in rk_iommu_probe()") +Cc: stable@vger.kernel.org +Signed-off-by: Sandy Huang +Signed-off-by: Heiko Stuebner +Tested-by: Ezequiel Garcia +Reviewed-by: Tomasz Figa +Reviewed-by: Marc Zyngier +Link: https://patchwork.freedesktop.org/patch/msgid/20180612132028.27490-3-heiko@sntech.de +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 25 +++++++++++++++++-------- + 1 file changed, 17 insertions(+), 8 deletions(-) + +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -573,8 +573,6 @@ static int vop_enable(struct drm_crtc *c + + spin_unlock(&vop->reg_lock); + +- enable_irq(vop->irq); +- + drm_crtc_vblank_on(crtc); + + return 0; +@@ -618,8 +616,6 @@ static void vop_crtc_atomic_disable(stru + + vop_dsp_hold_valid_irq_disable(vop); + +- disable_irq(vop->irq); +- + vop->is_enabled = false; + + /* +@@ -1196,6 +1192,18 @@ static irqreturn_t vop_isr(int irq, void + int ret = IRQ_NONE; + + /* ++ * The irq is shared with the iommu. If the runtime-pm state of the ++ * vop-device is disabled the irq has to be targeted at the iommu. ++ */ ++ if (!pm_runtime_get_if_in_use(vop->dev)) ++ return IRQ_NONE; ++ ++ if (vop_core_clks_enable(vop)) { ++ DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n"); ++ goto out; ++ } ++ ++ /* + * interrupt register has interrupt status, enable and clear bits, we + * must hold irq_lock to avoid a race with enable/disable_vblank(). + */ +@@ -1210,7 +1218,7 @@ static irqreturn_t vop_isr(int irq, void + + /* This is expected for vop iommu irqs, since the irq is shared */ + if (!active_irqs) +- return IRQ_NONE; ++ goto out_disable; + + if (active_irqs & DSP_HOLD_VALID_INTR) { + complete(&vop->dsp_hold_completion); +@@ -1236,6 +1244,10 @@ static irqreturn_t vop_isr(int irq, void + DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n", + active_irqs); + ++out_disable: ++ vop_core_clks_disable(vop); ++out: ++ pm_runtime_put(vop->dev); + return ret; + } + +@@ -1614,9 +1626,6 @@ static int vop_bind(struct device *dev, + if (ret) + goto err_disable_pm_runtime; + +- /* IRQ is initially disabled; it gets enabled in power_on */ +- disable_irq(vop->irq); +- + return 0; + + err_disable_pm_runtime: diff --git a/queue-4.18/drm-rockchip-vop-split-out-core-clock-enablement-into-separate-functions.patch b/queue-4.18/drm-rockchip-vop-split-out-core-clock-enablement-into-separate-functions.patch new file mode 100644 index 00000000000..7f7bdcc7b8d --- /dev/null +++ b/queue-4.18/drm-rockchip-vop-split-out-core-clock-enablement-into-separate-functions.patch @@ -0,0 +1,114 @@ +From e2810a7167df14c762e085fae5aade38425b71bf Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Tue, 12 Jun 2018 15:20:27 +0200 +Subject: drm/rockchip: vop: split out core clock enablement into separate functions + +From: Heiko Stuebner + +commit e2810a7167df14c762e085fae5aade38425b71bf upstream. + +Judging from the iommu code, both the hclk and aclk are necessary for +register access. Split them off into separate functions from the regular +vop enablement, so that we can use them elsewhere as well. + +Fixes: d0b912bd4c23 ("iommu/rockchip: Request irqs in rk_iommu_probe()") +[prerequisite change for the actual fix] +Cc: stable@vger.kernel.org +Signed-off-by: Heiko Stuebner +Tested-by: Ezequiel Garcia +Reviewed-by: Tomasz Figa +Link: https://patchwork.freedesktop.org/patch/msgid/20180612132028.27490-2-heiko@sntech.de +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 44 +++++++++++++++++++--------- + 1 file changed, 31 insertions(+), 13 deletions(-) + +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -486,6 +486,31 @@ static void vop_line_flag_irq_disable(st + spin_unlock_irqrestore(&vop->irq_lock, flags); + } + ++static int vop_core_clks_enable(struct vop *vop) ++{ ++ int ret; ++ ++ ret = clk_enable(vop->hclk); ++ if (ret < 0) ++ return ret; ++ ++ ret = clk_enable(vop->aclk); ++ if (ret < 0) ++ goto err_disable_hclk; ++ ++ return 0; ++ ++err_disable_hclk: ++ clk_disable(vop->hclk); ++ return ret; ++} ++ ++static void vop_core_clks_disable(struct vop *vop) ++{ ++ clk_disable(vop->aclk); ++ clk_disable(vop->hclk); ++} ++ + static int vop_enable(struct drm_crtc *crtc) + { + struct vop *vop = to_vop(crtc); +@@ -497,17 +522,13 @@ static int vop_enable(struct drm_crtc *c + return ret; + } + +- ret = clk_enable(vop->hclk); ++ ret = vop_core_clks_enable(vop); + if (WARN_ON(ret < 0)) + goto err_put_pm_runtime; + + ret = clk_enable(vop->dclk); + if (WARN_ON(ret < 0)) +- goto err_disable_hclk; +- +- ret = clk_enable(vop->aclk); +- if (WARN_ON(ret < 0)) +- goto err_disable_dclk; ++ goto err_disable_core; + + /* + * Slave iommu shares power, irq and clock with vop. It was associated +@@ -519,7 +540,7 @@ static int vop_enable(struct drm_crtc *c + if (ret) { + DRM_DEV_ERROR(vop->dev, + "failed to attach dma mapping, %d\n", ret); +- goto err_disable_aclk; ++ goto err_disable_dclk; + } + + spin_lock(&vop->reg_lock); +@@ -558,12 +579,10 @@ static int vop_enable(struct drm_crtc *c + + return 0; + +-err_disable_aclk: +- clk_disable(vop->aclk); + err_disable_dclk: + clk_disable(vop->dclk); +-err_disable_hclk: +- clk_disable(vop->hclk); ++err_disable_core: ++ vop_core_clks_disable(vop); + err_put_pm_runtime: + pm_runtime_put_sync(vop->dev); + return ret; +@@ -609,8 +628,7 @@ static void vop_crtc_atomic_disable(stru + rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev); + + clk_disable(vop->dclk); +- clk_disable(vop->aclk); +- clk_disable(vop->hclk); ++ vop_core_clks_disable(vop); + pm_runtime_put(vop->dev); + mutex_unlock(&vop->vop_lock); + diff --git a/queue-4.18/mm-respect-arch_dup_mmap-return-value.patch b/queue-4.18/mm-respect-arch_dup_mmap-return-value.patch new file mode 100644 index 00000000000..a22cd17889f --- /dev/null +++ b/queue-4.18/mm-respect-arch_dup_mmap-return-value.patch @@ -0,0 +1,42 @@ +From 1ed0cc5a01a4d868d9907ce96468c4b4c6709556 Mon Sep 17 00:00:00 2001 +From: Nadav Amit +Date: Tue, 4 Sep 2018 15:45:41 -0700 +Subject: mm: respect arch_dup_mmap() return value + +From: Nadav Amit + +commit 1ed0cc5a01a4d868d9907ce96468c4b4c6709556 upstream. + +Commit d70f2a14b72a ("include/linux/sched/mm.h: uninline mmdrop_async(), +etc") ignored the return value of arch_dup_mmap(). As a result, on x86, +a failure to duplicate the LDT (e.g. due to memory allocation error) +would leave the duplicated memory mapping in an inconsistent state. + +Fix by using the return value, as it was before the change. + +Link: http://lkml.kernel.org/r/20180823051229.211856-1-namit@vmware.com +Fixes: d70f2a14b72a4 ("include/linux/sched/mm.h: uninline mmdrop_async(), etc") +Signed-off-by: Nadav Amit +Acked-by: Michal Hocko +Cc: +Signed-off-by: Greg Kroah-Hartman + +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds + +--- + kernel/fork.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/kernel/fork.c ++++ b/kernel/fork.c +@@ -549,8 +549,7 @@ static __latent_entropy int dup_mmap(str + goto out; + } + /* a new mm has just been created */ +- arch_dup_mmap(oldmm, mm); +- retval = 0; ++ retval = arch_dup_mmap(oldmm, mm); + out: + up_write(&mm->mmap_sem); + flush_tlb_mm(oldmm); diff --git a/queue-4.18/series b/queue-4.18/series index 76acba4a268..a8188baa0cc 100644 --- a/queue-4.18/series +++ b/queue-4.18/series @@ -158,4 +158,29 @@ drm-i915-free-write_buf-that-we-allocated-with-kzalloc.patch drm-amdgpu-update-uvd_v6_0_ring_vm_funcs-to-use-new-nop-packet.patch drm-amdgpu-fix-a-reversed-condition.patch drm-amdgpu-fix-rlc-safe-mode-test-in-gfx_v9_0_enter_rlc_safe_mode.patch +drm-amd-pp-convert-voltage-unit-in-mv-4-to-mv-on-cz-st.patch +drm-amd-powerplay-fixed-uninitialized-value.patch +drm-amd-pp-polaris12-fix-a-chunk-of-registers-missed-to-program.patch +drm-edid-quirk-vive-pro-vr-headset-non-desktop.patch +drm-edid-add-6-bpc-quirk-for-sdc-panel-in-lenovo-b50-80.patch +drm-amd-display-fix-type-of-variable.patch +drm-amd-display-don-t-share-clk-source-between-dp-and-hdmi.patch +drm-amd-display-update-clk-for-various-hdmi-color-depths.patch +drm-amd-display-use-requested-hdmi-aspect-ratio.patch +drm-amd-display-report-non-dp-display-as-disconnected-without-edid.patch +drm-rockchip-lvds-add-missing-of_node_put.patch +drm-rockchip-vop-split-out-core-clock-enablement-into-separate-functions.patch +drm-rockchip-vop-fix-irq-disabled-after-vop-driver-probed.patch +drm-amd-display-pass-connector-id-when-executing-vbios-ct.patch +drm-amd-display-check-if-clock-source-in-use-before-disabling.patch +drm-amdgpu-update-tmr-mc-address.patch +drm-amdgpu-add-tmr-mc-address-into-amdgpu_firmware_info.patch +drm-amdgpu-add-new-firmware-id-for-vcn.patch +drm-amdgpu-add-vcn-support-in-psp-driver.patch +drm-amdgpu-add-vcn-booting-with-firmware-loaded-by-psp.patch +drm-amdgpu-fix-incorrect-use-of-fcheck.patch +drm-amdgpu-fix-incorrect-use-of-drm_file-pid.patch +drm-i915-re-apply-perform-link-quality-check-unconditionally-during-long-pulse.patch +uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch +mm-respect-arch_dup_mmap-return-value.patch drm-i915-glk-add-quirk-for-glk-nuc-hdmi-port-issues.patch diff --git a/queue-4.18/uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch b/queue-4.18/uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch new file mode 100644 index 00000000000..2b8a6992eab --- /dev/null +++ b/queue-4.18/uapi-linux-keyctl.h-don-t-use-c-reserved-keyword-as-a-struct-member-name.patch @@ -0,0 +1,55 @@ +From 8a2336e549d385bb0b46880435b411df8d8200e8 Mon Sep 17 00:00:00 2001 +From: Randy Dunlap +Date: Tue, 4 Sep 2018 15:46:13 -0700 +Subject: uapi/linux/keyctl.h: don't use C++ reserved keyword as a struct member name + +From: Randy Dunlap + +commit 8a2336e549d385bb0b46880435b411df8d8200e8 upstream. + +Since this header is in "include/uapi/linux/", apparently people want to +use it in userspace programs -- even in C++ ones. However, the header +uses a C++ reserved keyword ("private"), so change that to "dh_private" +instead to allow the header file to be used in C++ userspace. + +Fixes https://bugzilla.kernel.org/show_bug.cgi?id=191051 +Link: http://lkml.kernel.org/r/0db6c314-1ef4-9bfa-1baa-7214dd2ee061@infradead.org +Fixes: ddbb41148724 ("KEYS: Add KEYCTL_DH_COMPUTE command") +Signed-off-by: Randy Dunlap +Reviewed-by: Andrew Morton +Cc: David Howells +Cc: James Morris +Cc: "Serge E. Hallyn" +Cc: Mat Martineau +Cc: +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman + +--- + include/uapi/linux/keyctl.h | 2 +- + security/keys/dh.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/include/uapi/linux/keyctl.h ++++ b/include/uapi/linux/keyctl.h +@@ -65,7 +65,7 @@ + + /* keyctl structures */ + struct keyctl_dh_params { +- __s32 private; ++ __s32 dh_private; + __s32 prime; + __s32 base; + }; +--- a/security/keys/dh.c ++++ b/security/keys/dh.c +@@ -300,7 +300,7 @@ long __keyctl_dh_compute(struct keyctl_d + } + dh_inputs.g_size = dlen; + +- dlen = dh_data_from_key(pcopy.private, &dh_inputs.key); ++ dlen = dh_data_from_key(pcopy.dh_private, &dh_inputs.key); + if (dlen < 0) { + ret = dlen; + goto out2;