From: Greg Kroah-Hartman Date: Thu, 14 Jun 2012 22:26:58 +0000 (-0700) Subject: 3.4-stable patches X-Git-Tag: v3.0.35~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=67ae4f666c8f5be265fd3850bdb93743735a7d46;p=thirdparty%2Fkernel%2Fstable-queue.git 3.4-stable patches added patches: ata_piix-defer-disks-to-the-hyper-v-drivers-by-default.patch drm-i915-mark-the-ringbuffers-as-being-in-the-gtt-domain.patch drm-radeon-fix-tiling-and-command-stream-checking-on-evergreen-v3.patch fuse-fix-stat-call-on-32-bit-platforms.patch libata-add-a-host-flag-to-ignore-detected-ata-devices.patch sched-fix-the-relax_domain_level-boot-parameter.patch --- diff --git a/queue-3.4/ata_piix-defer-disks-to-the-hyper-v-drivers-by-default.patch b/queue-3.4/ata_piix-defer-disks-to-the-hyper-v-drivers-by-default.patch new file mode 100644 index 00000000000..abaed95e113 --- /dev/null +++ b/queue-3.4/ata_piix-defer-disks-to-the-hyper-v-drivers-by-default.patch @@ -0,0 +1,82 @@ +From cd006086fa5d91414d8ff9ff2b78fbb593878e3c Mon Sep 17 00:00:00 2001 +From: Andy Whitcroft +Date: Fri, 4 May 2012 22:15:11 +0100 +Subject: ata_piix: defer disks to the Hyper-V drivers by default + +From: Andy Whitcroft + +commit cd006086fa5d91414d8ff9ff2b78fbb593878e3c upstream. + +When we are hosted on a Microsoft Hyper-V hypervisor the guest disks +are exposed both via the Hyper-V paravirtualised drivers and via an +emulated SATA disk drive. In this case we want to use the paravirtualised +drivers if we can as they are much more efficient. Note that the Hyper-V +paravirtualised drivers only expose the virtual hard disk devices, the +CDROM/DVD devices must still be enumerated. + +Mark the host controller ATA_HOST_IGNORE_ATA to prevent enumeration of +disk devices. + +BugLink: http://bugs.launchpad.net/bugs/929545 +BugLink: http://bugs.launchpad.net/bugs/942316 +Signed-off-by: Andy Whitcroft +Signed-off-by: Jeff Garzik +Cc: Victor Miasnikov +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/ata/ata_piix.c | 36 ++++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +--- a/drivers/ata/ata_piix.c ++++ b/drivers/ata/ata_piix.c +@@ -1554,6 +1554,39 @@ static bool piix_broken_system_poweroff( + return false; + } + ++static int prefer_ms_hyperv = 1; ++module_param(prefer_ms_hyperv, int, 0); ++ ++static void piix_ignore_devices_quirk(struct ata_host *host) ++{ ++#if IS_ENABLED(CONFIG_HYPERV_STORAGE) ++ static const struct dmi_system_id ignore_hyperv[] = { ++ { ++ /* On Hyper-V hypervisors the disks are exposed on ++ * both the emulated SATA controller and on the ++ * paravirtualised drivers. The CD/DVD devices ++ * are only exposed on the emulated controller. ++ * Request we ignore ATA devices on this host. ++ */ ++ .ident = "Hyper-V Virtual Machine", ++ .matches = { ++ DMI_MATCH(DMI_SYS_VENDOR, ++ "Microsoft Corporation"), ++ DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"), ++ }, ++ }, ++ { } /* terminate list */ ++ }; ++ const struct dmi_system_id *dmi = dmi_first_match(ignore_hyperv); ++ ++ if (dmi && prefer_ms_hyperv) { ++ host->flags |= ATA_HOST_IGNORE_ATA; ++ dev_info(host->dev, "%s detected, ATA device ignore set\n", ++ dmi->ident); ++ } ++#endif ++} ++ + /** + * piix_init_one - Register PIIX ATA PCI device with kernel services + * @pdev: PCI device to register +@@ -1669,6 +1702,9 @@ static int __devinit piix_init_one(struc + } + host->flags |= ATA_HOST_PARALLEL_SCAN; + ++ /* Allow hosts to specify device types to ignore when scanning. */ ++ piix_ignore_devices_quirk(host); ++ + pci_set_master(pdev); + return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); + } diff --git a/queue-3.4/drm-i915-mark-the-ringbuffers-as-being-in-the-gtt-domain.patch b/queue-3.4/drm-i915-mark-the-ringbuffers-as-being-in-the-gtt-domain.patch new file mode 100644 index 00000000000..53695a91182 --- /dev/null +++ b/queue-3.4/drm-i915-mark-the-ringbuffers-as-being-in-the-gtt-domain.patch @@ -0,0 +1,41 @@ +From 3eef8918ff440837f6af791942d8dd07e1a268ee Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Mon, 4 Jun 2012 17:05:40 +0100 +Subject: drm/i915: Mark the ringbuffers as being in the GTT domain + +From: Chris Wilson + +commit 3eef8918ff440837f6af791942d8dd07e1a268ee upstream. + +By correctly describing the rinbuffers as being in the GTT domain, it +appears that we are more careful with the management of the CPU cache +upon resume and so prevent some coherency issue when submitting commands +to the GPU later. A secondary effect is that the debug logs are then +consistent with the actual usage (i.e. they no longer describe the +ringbuffers as being in the CPU write domain when we are accessing them +through an wc iomapping.) + +Reported-and-tested-by: Daniel Gnoutcheff +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41092 +Signed-off-by: Chris Wilson +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + + +--- + drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_ringbuffer.c ++++ b/drivers/gpu/drm/i915/intel_ringbuffer.c +@@ -1027,6 +1027,10 @@ int intel_init_ring_buffer(struct drm_de + if (ret) + goto err_unref; + ++ ret = i915_gem_object_set_to_gtt_domain(obj, true); ++ if (ret) ++ goto err_unpin; ++ + ring->map.size = ring->size; + ring->map.offset = dev->agp->base + obj->gtt_offset; + ring->map.type = 0; diff --git a/queue-3.4/drm-radeon-fix-tiling-and-command-stream-checking-on-evergreen-v3.patch b/queue-3.4/drm-radeon-fix-tiling-and-command-stream-checking-on-evergreen-v3.patch new file mode 100644 index 00000000000..311e8430036 --- /dev/null +++ b/queue-3.4/drm-radeon-fix-tiling-and-command-stream-checking-on-evergreen-v3.patch @@ -0,0 +1,174 @@ +From d26098759cf6d32148649c165f87a7590bc25b89 Mon Sep 17 00:00:00 2001 +From: Jerome Glisse +Date: Sat, 9 Jun 2012 10:57:41 -0400 +Subject: drm/radeon: fix tiling and command stream checking on evergreen v3 + +From: Jerome Glisse + +commit d26098759cf6d32148649c165f87a7590bc25b89 upstream. + +Fix regresson since the introduction of command stream checking on +evergreen (thread referenced below). Issue is cause by ddx allocating +bo with formula width*height*bpp while programming the GPU command +stream with ALIGN(height, 8). In some case (where page alignment does +not hide the extra size bo should be according to height alignment) +the kernel will reject the command stream. + +This patch reprogram the command stream to slice - 1 (slice is +a derivative value from height) which avoid rejecting the command +stream while keeping the value of command stream checking from a +security point of view. + +This patch also fix wrong computation of layer size for 2D tiled +surface. Which should fix issue when 2D color tiling is enabled. +This dump the radeon KMS_DRIVER_MINOR so userspace can know if +they are on a fixed kernel or not. + +https://lkml.org/lkml/2012/6/3/80 +https://bugs.freedesktop.org/show_bug.cgi?id=50892 +https://bugs.freedesktop.org/show_bug.cgi?id=50857 + +!!! STABLE need a custom version of this patch for 3.4 !!! + +v2: actually bump the minor version and add comment about stable +v3: do compute the height the ddx was trying to use + +[airlied: drop left over debug] + +Signed-off-by: Jerome Glisse +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/evergreen_cs.c | 49 +++++++++++++++++++++++++++++++--- + drivers/gpu/drm/radeon/radeon_drv.c | 3 +- + 2 files changed, 47 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/radeon/evergreen_cs.c ++++ b/drivers/gpu/drm/radeon/evergreen_cs.c +@@ -52,6 +52,7 @@ struct evergreen_cs_track { + u32 cb_color_view[12]; + u32 cb_color_pitch[12]; + u32 cb_color_slice[12]; ++ u32 cb_color_slice_idx[12]; + u32 cb_color_attrib[12]; + u32 cb_color_cmask_slice[8];/* unused */ + u32 cb_color_fmask_slice[8];/* unused */ +@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(stru + track->cb_color_info[i] = 0; + track->cb_color_view[i] = 0xFFFFFFFF; + track->cb_color_pitch[i] = 0; +- track->cb_color_slice[i] = 0; ++ track->cb_color_slice[i] = 0xfffffff; ++ track->cb_color_slice_idx[i] = 0; + } + track->cb_target_mask = 0xFFFFFFFF; + track->cb_shader_mask = 0xFFFFFFFF; + track->cb_dirty = true; + ++ track->db_depth_slice = 0xffffffff; + track->db_depth_view = 0xFFFFC000; + track->db_depth_size = 0xFFFFFFFF; + track->db_depth_control = 0xFFFFFFFF; +@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(st + { + struct evergreen_cs_track *track = p->track; + unsigned palign, halign, tileb, slice_pt; ++ unsigned mtile_pr, mtile_ps, mtileb; + + tileb = 64 * surf->bpe * surf->nsamples; +- palign = track->group_size / (8 * surf->bpe * surf->nsamples); +- palign = MAX(8, palign); + slice_pt = 1; + if (tileb > surf->tsplit) { + slice_pt = tileb / surf->tsplit; +@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(st + /* macro tile width & height */ + palign = (8 * surf->bankw * track->npipes) * surf->mtilea; + halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; +- surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt; ++ mtileb = (palign / 8) * (halign / 8) * tileb;; ++ mtile_pr = surf->nbx / palign; ++ mtile_ps = (mtile_pr * surf->nby) / halign; ++ surf->layer_size = mtile_ps * mtileb * slice_pt; + surf->base_align = (palign / 8) * (halign / 8) * tileb; + surf->palign = palign; + surf->halign = halign; +@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_c + + offset += surf.layer_size * mslice; + if (offset > radeon_bo_size(track->cb_color_bo[id])) { ++ /* old ddx are broken they allocate bo with w*h*bpp but ++ * program slice with ALIGN(h, 8), catch this and patch ++ * command stream. ++ */ ++ if (!surf.mode) { ++ volatile u32 *ib = p->ib->ptr; ++ unsigned long tmp, nby, bsize, size, min = 0; ++ ++ /* find the height the ddx wants */ ++ if (surf.nby > 8) { ++ min = surf.nby - 8; ++ } ++ bsize = radeon_bo_size(track->cb_color_bo[id]); ++ tmp = track->cb_color_bo_offset[id] << 8; ++ for (nby = surf.nby; nby > min; nby--) { ++ size = nby * surf.nbx * surf.bpe * surf.nsamples; ++ if ((tmp + size * mslice) <= bsize) { ++ break; ++ } ++ } ++ if (nby > min) { ++ surf.nby = nby; ++ slice = ((nby * surf.nbx) / 64) - 1; ++ if (!evergreen_surface_check(p, &surf, "cb")) { ++ /* check if this one works */ ++ tmp += surf.layer_size * mslice; ++ if (tmp <= bsize) { ++ ib[track->cb_color_slice_idx[id]] = slice; ++ goto old_ddx_ok; ++ } ++ } ++ } ++ } + dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " + "offset %d, max layer %d, bo size %ld, slice %d)\n", + __func__, __LINE__, id, surf.layer_size, +@@ -446,6 +484,7 @@ static int evergreen_cs_track_validate_c + surf.tsplit, surf.mtilea); + return -EINVAL; + } ++old_ddx_ok: + + return 0; + } +@@ -1532,6 +1571,7 @@ static int evergreen_cs_check_reg(struct + case CB_COLOR7_SLICE: + tmp = (reg - CB_COLOR0_SLICE) / 0x3c; + track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); ++ track->cb_color_slice_idx[tmp] = idx; + track->cb_dirty = true; + break; + case CB_COLOR8_SLICE: +@@ -1540,6 +1580,7 @@ static int evergreen_cs_check_reg(struct + case CB_COLOR11_SLICE: + tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; + track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); ++ track->cb_color_slice_idx[tmp] = idx; + track->cb_dirty = true; + break; + case CB_COLOR0_ATTRIB: +--- a/drivers/gpu/drm/radeon/radeon_drv.c ++++ b/drivers/gpu/drm/radeon/radeon_drv.c +@@ -57,9 +57,10 @@ + * 2.13.0 - virtual memory support, streamout + * 2.14.0 - add evergreen tiling informations + * 2.15.0 - add max_pipes query ++ * 2.16.0 - fix evergreen 2D tiled surface calculation + */ + #define KMS_DRIVER_MAJOR 2 +-#define KMS_DRIVER_MINOR 15 ++#define KMS_DRIVER_MINOR 16 + #define KMS_DRIVER_PATCHLEVEL 0 + int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); + int radeon_driver_unload_kms(struct drm_device *dev); diff --git a/queue-3.4/fuse-fix-stat-call-on-32-bit-platforms.patch b/queue-3.4/fuse-fix-stat-call-on-32-bit-platforms.patch new file mode 100644 index 00000000000..8ed12bed1a4 --- /dev/null +++ b/queue-3.4/fuse-fix-stat-call-on-32-bit-platforms.patch @@ -0,0 +1,97 @@ +From 45c72cd73c788dd18c8113d4a404d6b4a01decf1 Mon Sep 17 00:00:00 2001 +From: Pavel Shilovsky +Date: Thu, 10 May 2012 19:49:38 +0400 +Subject: fuse: fix stat call on 32 bit platforms + +From: Pavel Shilovsky + +commit 45c72cd73c788dd18c8113d4a404d6b4a01decf1 upstream. + +Now we store attr->ino at inode->i_ino, return attr->ino at the +first time and then return inode->i_ino if the attribute timeout +isn't expired. That's wrong on 32 bit platforms because attr->ino +is 64 bit and inode->i_ino is 32 bit in this case. + +Fix this by saving 64 bit ino in fuse_inode structure and returning +it every time we call getattr. Also squash attr->ino into inode->i_ino +explicitly. + +Signed-off-by: Pavel Shilovsky +Signed-off-by: Miklos Szeredi +Signed-off-by: Greg Kroah-Hartman + +--- + fs/fuse/dir.c | 1 + + fs/fuse/fuse_i.h | 3 +++ + fs/fuse/inode.c | 17 ++++++++++++++++- + 3 files changed, 20 insertions(+), 1 deletion(-) + +--- a/fs/fuse/dir.c ++++ b/fs/fuse/dir.c +@@ -863,6 +863,7 @@ int fuse_update_attributes(struct inode + if (stat) { + generic_fillattr(inode, stat); + stat->mode = fi->orig_i_mode; ++ stat->ino = fi->orig_ino; + } + } + +--- a/fs/fuse/fuse_i.h ++++ b/fs/fuse/fuse_i.h +@@ -82,6 +82,9 @@ struct fuse_inode { + preserve the original mode */ + umode_t orig_i_mode; + ++ /** 64 bit inode number */ ++ u64 orig_ino; ++ + /** Version of last attribute change */ + u64 attr_version; + +--- a/fs/fuse/inode.c ++++ b/fs/fuse/inode.c +@@ -91,6 +91,7 @@ static struct inode *fuse_alloc_inode(st + fi->nlookup = 0; + fi->attr_version = 0; + fi->writectr = 0; ++ fi->orig_ino = 0; + INIT_LIST_HEAD(&fi->write_files); + INIT_LIST_HEAD(&fi->queued_writes); + INIT_LIST_HEAD(&fi->writepages); +@@ -139,6 +140,18 @@ static int fuse_remount_fs(struct super_ + return 0; + } + ++/* ++ * ino_t is 32-bits on 32-bit arch. We have to squash the 64-bit value down ++ * so that it will fit. ++ */ ++static ino_t fuse_squash_ino(u64 ino64) ++{ ++ ino_t ino = (ino_t) ino64; ++ if (sizeof(ino_t) < sizeof(u64)) ++ ino ^= ino64 >> (sizeof(u64) - sizeof(ino_t)) * 8; ++ return ino; ++} ++ + void fuse_change_attributes_common(struct inode *inode, struct fuse_attr *attr, + u64 attr_valid) + { +@@ -148,7 +161,7 @@ void fuse_change_attributes_common(struc + fi->attr_version = ++fc->attr_version; + fi->i_time = attr_valid; + +- inode->i_ino = attr->ino; ++ inode->i_ino = fuse_squash_ino(attr->ino); + inode->i_mode = (inode->i_mode & S_IFMT) | (attr->mode & 07777); + set_nlink(inode, attr->nlink); + inode->i_uid = attr->uid; +@@ -174,6 +187,8 @@ void fuse_change_attributes_common(struc + fi->orig_i_mode = inode->i_mode; + if (!(fc->flags & FUSE_DEFAULT_PERMISSIONS)) + inode->i_mode &= ~S_ISVTX; ++ ++ fi->orig_ino = attr->ino; + } + + void fuse_change_attributes(struct inode *inode, struct fuse_attr *attr, diff --git a/queue-3.4/libata-add-a-host-flag-to-ignore-detected-ata-devices.patch b/queue-3.4/libata-add-a-host-flag-to-ignore-detected-ata-devices.patch new file mode 100644 index 00000000000..f160183f97c --- /dev/null +++ b/queue-3.4/libata-add-a-host-flag-to-ignore-detected-ata-devices.patch @@ -0,0 +1,48 @@ +From db63a4c8115a0bb904496e1cdd3e7488e68b0d06 Mon Sep 17 00:00:00 2001 +From: Andy Whitcroft +Date: Fri, 4 May 2012 22:15:10 +0100 +Subject: libata: add a host flag to ignore detected ATA devices + +From: Andy Whitcroft + +commit db63a4c8115a0bb904496e1cdd3e7488e68b0d06 upstream. + +Where devices are visible via more than one host we sometimes wish to +indicate that cirtain devices should be ignored on a specific host. Add a +host flag indicating that this host wishes to ignore ATA specific devices. + +Signed-off-by: Andy Whitcroft +Signed-off-by: Jeff Garzik +Cc: Victor Miasnikov +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/ata/libata-core.c | 6 ++++++ + include/linux/libata.h | 1 + + 2 files changed, 7 insertions(+) + +--- a/drivers/ata/libata-core.c ++++ b/drivers/ata/libata-core.c +@@ -1973,6 +1973,12 @@ retry: + if (class == ATA_DEV_ATA) { + if (!ata_id_is_ata(id) && !ata_id_is_cfa(id)) + goto err_out; ++ if (ap->host->flags & ATA_HOST_IGNORE_ATA && ++ ata_id_is_ata(id)) { ++ ata_dev_dbg(dev, ++ "host indicates ignore ATA devices, ignored\n"); ++ return -ENOENT; ++ } + } else { + if (ata_id_is_ata(id)) + goto err_out; +--- a/include/linux/libata.h ++++ b/include/linux/libata.h +@@ -247,6 +247,7 @@ enum { + ATA_HOST_SIMPLEX = (1 << 0), /* Host is simplex, one DMA channel per host only */ + ATA_HOST_STARTED = (1 << 1), /* Host started */ + ATA_HOST_PARALLEL_SCAN = (1 << 2), /* Ports on this host can be scanned in parallel */ ++ ATA_HOST_IGNORE_ATA = (1 << 3), /* Ignore ATA devices on this host. */ + + /* bits 24:31 of host->flags are reserved for LLD specific flags */ + diff --git a/queue-3.4/sched-fix-the-relax_domain_level-boot-parameter.patch b/queue-3.4/sched-fix-the-relax_domain_level-boot-parameter.patch new file mode 100644 index 00000000000..2439b5128b6 --- /dev/null +++ b/queue-3.4/sched-fix-the-relax_domain_level-boot-parameter.patch @@ -0,0 +1,62 @@ +From a841f8cef4bb124f0f5563314d0beaf2e1249d72 Mon Sep 17 00:00:00 2001 +From: Dimitri Sivanich +Date: Tue, 5 Jun 2012 13:44:36 -0500 +Subject: sched: Fix the relax_domain_level boot parameter + +From: Dimitri Sivanich + +commit a841f8cef4bb124f0f5563314d0beaf2e1249d72 upstream. + +It does not get processed because sched_domain_level_max is 0 at the +time that setup_relax_domain_level() is run. + +Simply accept the value as it is, as we don't know the value of +sched_domain_level_max until sched domain construction is completed. + +Fix sched_relax_domain_level in cpuset. The build_sched_domain() routine calls +the set_domain_attribute() routine prior to setting the sd->level, however, +the set_domain_attribute() routine relies on the sd->level to decide whether +idle load balancing will be off/on. + +Signed-off-by: Dimitri Sivanich +Signed-off-by: Peter Zijlstra +Link: http://lkml.kernel.org/r/20120605184436.GA15668@sgi.com +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman + +--- + kernel/sched/core.c | 9 +++------ + 1 file changed, 3 insertions(+), 6 deletions(-) + +--- a/kernel/sched/core.c ++++ b/kernel/sched/core.c +@@ -6230,11 +6230,8 @@ int sched_domain_level_max; + + static int __init setup_relax_domain_level(char *str) + { +- unsigned long val; +- +- val = simple_strtoul(str, NULL, 0); +- if (val < sched_domain_level_max) +- default_relax_domain_level = val; ++ if (kstrtoint(str, 0, &default_relax_domain_level)) ++ pr_warn("Unable to set relax_domain_level\n"); + + return 1; + } +@@ -6439,7 +6436,6 @@ struct sched_domain *build_sched_domain( + if (!sd) + return child; + +- set_domain_attribute(sd, attr); + cpumask_and(sched_domain_span(sd), cpu_map, tl->mask(cpu)); + if (child) { + sd->level = child->level + 1; +@@ -6447,6 +6443,7 @@ struct sched_domain *build_sched_domain( + child->parent = sd; + } + sd->child = child; ++ set_domain_attribute(sd, attr); + + return sd; + } diff --git a/queue-3.4/series b/queue-3.4/series index 67f3e186af4..ee92cad69d9 100644 --- a/queue-3.4/series +++ b/queue-3.4/series @@ -34,3 +34,9 @@ can-c_can-fix-an-interrupt-thrash-issue-with-c_can-driver.patch can-c_can-fix-race-condition-in-c_can_open.patch gma500-don-t-register-the-acpi-video-bus.patch acpi_video-fix-leaking-pci-references.patch +sched-fix-the-relax_domain_level-boot-parameter.patch +drm-radeon-fix-tiling-and-command-stream-checking-on-evergreen-v3.patch +drm-i915-mark-the-ringbuffers-as-being-in-the-gtt-domain.patch +fuse-fix-stat-call-on-32-bit-platforms.patch +libata-add-a-host-flag-to-ignore-detected-ata-devices.patch +ata_piix-defer-disks-to-the-hyper-v-drivers-by-default.patch