From: Sasha Levin Date: Fri, 28 Aug 2020 22:49:19 +0000 (-0400) Subject: Fixes for 5.8 X-Git-Tag: v4.4.235~59 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=67d226d39899787c75be0b972cd0db1f1ccd8c69;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.8 Signed-off-by: Sasha Levin --- diff --git a/queue-5.8/alsa-usb-audio-add-capture-support-for-saffire-6-usb.patch b/queue-5.8/alsa-usb-audio-add-capture-support-for-saffire-6-usb.patch new file mode 100644 index 00000000000..b0d5f4af08d --- /dev/null +++ b/queue-5.8/alsa-usb-audio-add-capture-support-for-saffire-6-usb.patch @@ -0,0 +1,75 @@ +From 32976a57f1517d3c414e516f34e7b66547927078 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 15 Aug 2020 03:21:03 +0300 +Subject: ALSA: usb-audio: Add capture support for Saffire 6 (USB 1.1) + +From: Alexander Tsoy + +[ Upstream commit 470757f5b3a46bd85741bb0d8c1fd3f21048a2af ] + +Capture and playback endpoints on Saffire 6 (USB 1.1) resides on the same +interface. This was not supported by the composite quirk back in the day +when initial support for this device was added, thus only playback was +enabled until now. + +Fixes: 11e424e88bd4 ("ALSA: usb-audio: Add support for Focusrite Saffire 6 USB") +Signed-off-by: Alexander Tsoy +Cc: +Link: https://lore.kernel.org/r/20200815002103.29247-1-alexander@tsoy.me +Signed-off-by: Takashi Iwai +Signed-off-by: Sasha Levin +--- + sound/usb/quirks-table.h | 30 ++++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h +index a53eb67ad4bd8..946e7804942c7 100644 +--- a/sound/usb/quirks-table.h ++++ b/sound/usb/quirks-table.h +@@ -2678,6 +2678,10 @@ YAMAHA_DEVICE(0x7010, "UB99"), + .ifnum = QUIRK_ANY_INTERFACE, + .type = QUIRK_COMPOSITE, + .data = (const struct snd_usb_audio_quirk[]) { ++ { ++ .ifnum = 0, ++ .type = QUIRK_AUDIO_STANDARD_MIXER, ++ }, + { + .ifnum = 0, + .type = QUIRK_AUDIO_FIXED_ENDPOINT, +@@ -2690,6 +2694,32 @@ YAMAHA_DEVICE(0x7010, "UB99"), + .attributes = UAC_EP_CS_ATTR_SAMPLE_RATE, + .endpoint = 0x01, + .ep_attr = USB_ENDPOINT_XFER_ISOC, ++ .datainterval = 1, ++ .maxpacksize = 0x024c, ++ .rates = SNDRV_PCM_RATE_44100 | ++ SNDRV_PCM_RATE_48000, ++ .rate_min = 44100, ++ .rate_max = 48000, ++ .nr_rates = 2, ++ .rate_table = (unsigned int[]) { ++ 44100, 48000 ++ } ++ } ++ }, ++ { ++ .ifnum = 0, ++ .type = QUIRK_AUDIO_FIXED_ENDPOINT, ++ .data = &(const struct audioformat) { ++ .formats = SNDRV_PCM_FMTBIT_S24_3LE, ++ .channels = 2, ++ .iface = 0, ++ .altsetting = 1, ++ .altset_idx = 1, ++ .attributes = 0, ++ .endpoint = 0x82, ++ .ep_attr = USB_ENDPOINT_XFER_ISOC, ++ .datainterval = 1, ++ .maxpacksize = 0x0126, + .rates = SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_48000, + .rate_min = 44100, +-- +2.25.1 + diff --git a/queue-5.8/cpufreq-intel_pstate-fix-epp-setting-via-sysfs-in-ac.patch b/queue-5.8/cpufreq-intel_pstate-fix-epp-setting-via-sysfs-in-ac.patch new file mode 100644 index 00000000000..40f3c02a30a --- /dev/null +++ b/queue-5.8/cpufreq-intel_pstate-fix-epp-setting-via-sysfs-in-ac.patch @@ -0,0 +1,72 @@ +From b4abe2ece016e7d9e65f8c20448ca9fc18f99599 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 28 Jul 2020 19:09:32 +0200 +Subject: cpufreq: intel_pstate: Fix EPP setting via sysfs in active mode + +From: Rafael J. Wysocki + +[ Upstream commit de002c55cadfc2f6cdf0ed427526f6085d240238 ] + +Because intel_pstate_set_energy_pref_index() reads and writes the +MSR_HWP_REQUEST register without using the cached value of it used by +intel_pstate_hwp_boost_up() and intel_pstate_hwp_boost_down(), those +functions may overwrite the value written by it and so the EPP value +set via sysfs may be lost. + +To avoid that, make intel_pstate_set_energy_pref_index() take the +cached value of MSR_HWP_REQUEST just like the other two routines +mentioned above and update it with the new EPP value coming from +user space in addition to updating the MSR. + +Note that the MSR itself still needs to be updated too in case +hwp_boost is unset or the boosting mechanism is not active at the +EPP change time. + +Fixes: e0efd5be63e8 ("cpufreq: intel_pstate: Add HWP boost utility and sched util hooks") +Reported-by: Francisco Jerez +Cc: 4.18+ # 4.18+: 3da97d4db8ee cpufreq: intel_pstate: Rearrange ... +Signed-off-by: Rafael J. Wysocki +Reviewed-by: Francisco Jerez +Signed-off-by: Sasha Levin +--- + drivers/cpufreq/intel_pstate.c | 17 ++++++++++++----- + 1 file changed, 12 insertions(+), 5 deletions(-) + +diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c +index c7540ad28995b..2eea6db98cb5e 100644 +--- a/drivers/cpufreq/intel_pstate.c ++++ b/drivers/cpufreq/intel_pstate.c +@@ -649,11 +649,12 @@ static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, + mutex_lock(&intel_pstate_limits_lock); + + if (boot_cpu_has(X86_FEATURE_HWP_EPP)) { +- u64 value; +- +- ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); +- if (ret) +- goto return_pref; ++ /* ++ * Use the cached HWP Request MSR value, because the register ++ * itself may be updated by intel_pstate_hwp_boost_up() or ++ * intel_pstate_hwp_boost_down() at any time. ++ */ ++ u64 value = READ_ONCE(cpu_data->hwp_req_cached); + + value &= ~GENMASK_ULL(31, 24); + +@@ -661,6 +662,12 @@ static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, + epp = epp_values[pref_index - 1]; + + value |= (u64)epp << 24; ++ /* ++ * The only other updater of hwp_req_cached in the active mode, ++ * intel_pstate_hwp_set(), is called under the same lock as this ++ * function, so it cannot run in parallel with the update below. ++ */ ++ WRITE_ONCE(cpu_data->hwp_req_cached, value); + ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); + } else { + if (epp == -EINVAL) +-- +2.25.1 + diff --git a/queue-5.8/pci-qcom-add-missing-ipq806x-clocks-in-pcie-driver.patch b/queue-5.8/pci-qcom-add-missing-ipq806x-clocks-in-pcie-driver.patch new file mode 100644 index 00000000000..17306f10de4 --- /dev/null +++ b/queue-5.8/pci-qcom-add-missing-ipq806x-clocks-in-pcie-driver.patch @@ -0,0 +1,113 @@ +From f874efb64a0ee57e4e1b82724d72a1f5a0db7869 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 15 Jun 2020 23:05:57 +0200 +Subject: PCI: qcom: Add missing ipq806x clocks in PCIe driver + +From: Ansuel Smith + +[ Upstream commit 8b6f0330b5f9a7543356bfa9e76d580f03aa2c1e ] + +Aux and Ref clk are missing in PCIe qcom driver. Add support for this +optional clks for ipq8064/apq8064 SoC. + +Link: https://lore.kernel.org/r/20200615210608.21469-2-ansuelsmth@gmail.com +Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") +Signed-off-by: Sham Muthayyan +Signed-off-by: Ansuel Smith +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Rob Herring +Acked-by: Stanimir Varbanov +Signed-off-by: Sasha Levin +--- + drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++---- + 1 file changed, 33 insertions(+), 5 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c +index 5dd1740855770..aa25a3040f7cc 100644 +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -106,6 +106,8 @@ struct qcom_pcie_resources_2_1_0 { + struct clk *iface_clk; + struct clk *core_clk; + struct clk *phy_clk; ++ struct clk *aux_clk; ++ struct clk *ref_clk; + struct reset_control *pci_reset; + struct reset_control *axi_reset; + struct reset_control *ahb_reset; +@@ -264,6 +266,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) + if (IS_ERR(res->phy_clk)) + return PTR_ERR(res->phy_clk); + ++ res->aux_clk = devm_clk_get_optional(dev, "aux"); ++ if (IS_ERR(res->aux_clk)) ++ return PTR_ERR(res->aux_clk); ++ ++ res->ref_clk = devm_clk_get_optional(dev, "ref"); ++ if (IS_ERR(res->ref_clk)) ++ return PTR_ERR(res->ref_clk); ++ + res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); + if (IS_ERR(res->pci_reset)) + return PTR_ERR(res->pci_reset); +@@ -296,6 +306,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) + clk_disable_unprepare(res->iface_clk); + clk_disable_unprepare(res->core_clk); + clk_disable_unprepare(res->phy_clk); ++ clk_disable_unprepare(res->aux_clk); ++ clk_disable_unprepare(res->ref_clk); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + } + +@@ -326,16 +338,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) + goto err_assert_ahb; + } + ++ ret = clk_prepare_enable(res->core_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable core clock\n"); ++ goto err_clk_core; ++ } ++ + ret = clk_prepare_enable(res->phy_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable phy clock\n"); + goto err_clk_phy; + } + +- ret = clk_prepare_enable(res->core_clk); ++ ret = clk_prepare_enable(res->aux_clk); + if (ret) { +- dev_err(dev, "cannot prepare/enable core clock\n"); +- goto err_clk_core; ++ dev_err(dev, "cannot prepare/enable aux clock\n"); ++ goto err_clk_aux; ++ } ++ ++ ret = clk_prepare_enable(res->ref_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable ref clock\n"); ++ goto err_clk_ref; + } + + ret = reset_control_deassert(res->ahb_reset); +@@ -411,10 +435,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) + return 0; + + err_deassert_ahb: +- clk_disable_unprepare(res->core_clk); +-err_clk_core: ++ clk_disable_unprepare(res->ref_clk); ++err_clk_ref: ++ clk_disable_unprepare(res->aux_clk); ++err_clk_aux: + clk_disable_unprepare(res->phy_clk); + err_clk_phy: ++ clk_disable_unprepare(res->core_clk); ++err_clk_core: + clk_disable_unprepare(res->iface_clk); + err_assert_ahb: + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); +-- +2.25.1 + diff --git a/queue-5.8/pci-qcom-add-missing-reset-for-ipq806x.patch b/queue-5.8/pci-qcom-add-missing-reset-for-ipq806x.patch new file mode 100644 index 00000000000..e8c5e1901cf --- /dev/null +++ b/queue-5.8/pci-qcom-add-missing-reset-for-ipq806x.patch @@ -0,0 +1,72 @@ +From c0190690ddc7ce913a2c867d0f6d61687eb1ac4b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 15 Jun 2020 23:06:00 +0200 +Subject: PCI: qcom: Add missing reset for ipq806x + +From: Ansuel Smith + +[ Upstream commit ee367e2cdd2202b5714982739e684543cd2cee0e ] + +Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. + +Link: https://lore.kernel.org/r/20200615210608.21469-5-ansuelsmth@gmail.com +Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") +Signed-off-by: Sham Muthayyan +Signed-off-by: Ansuel Smith +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Rob Herring +Reviewed-by: Philipp Zabel +Acked-by: Stanimir Varbanov +Cc: stable@vger.kernel.org # v4.5+ +Signed-off-by: Sasha Levin +--- + drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c +index 20c917327a8bd..f38e710de4789 100644 +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -113,6 +113,7 @@ struct qcom_pcie_resources_2_1_0 { + struct reset_control *ahb_reset; + struct reset_control *por_reset; + struct reset_control *phy_reset; ++ struct reset_control *ext_reset; + struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; + }; + +@@ -290,6 +291,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) + if (IS_ERR(res->por_reset)) + return PTR_ERR(res->por_reset); + ++ res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext"); ++ if (IS_ERR(res->ext_reset)) ++ return PTR_ERR(res->ext_reset); ++ + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); + return PTR_ERR_OR_ZERO(res->phy_reset); + } +@@ -303,6 +308,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) + reset_control_assert(res->axi_reset); + reset_control_assert(res->ahb_reset); + reset_control_assert(res->por_reset); ++ reset_control_assert(res->ext_reset); + reset_control_assert(res->phy_reset); + clk_disable_unprepare(res->iface_clk); + clk_disable_unprepare(res->core_clk); +@@ -362,6 +368,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) + goto err_deassert_ahb; + } + ++ ret = reset_control_deassert(res->ext_reset); ++ if (ret) { ++ dev_err(dev, "cannot deassert ext reset\n"); ++ goto err_deassert_ahb; ++ } ++ + /* enable PCIe clocks and resets */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val &= ~BIT(0); +-- +2.25.1 + diff --git a/queue-5.8/pci-qcom-change-duplicate-pci-reset-to-phy-reset.patch b/queue-5.8/pci-qcom-change-duplicate-pci-reset-to-phy-reset.patch new file mode 100644 index 00000000000..245bc0a0f8c --- /dev/null +++ b/queue-5.8/pci-qcom-change-duplicate-pci-reset-to-phy-reset.patch @@ -0,0 +1,82 @@ +From 5dfcc99818d308d7da51437b9770d24d954f614c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 15 Jun 2020 23:05:59 +0200 +Subject: PCI: qcom: Change duplicate PCI reset to phy reset + +From: Abhishek Sahu + +[ Upstream commit dd58318c019f10bc94db36df66af6c55d4c0cbba ] + +The deinit issues reset_control_assert for PCI twice and does not contain +phy reset. + +Link: https://lore.kernel.org/r/20200615210608.21469-4-ansuelsmth@gmail.com +Signed-off-by: Abhishek Sahu +Signed-off-by: Ansuel Smith +Signed-off-by: Lorenzo Pieralisi +Reviewed-by: Rob Herring +Acked-by: Stanimir Varbanov +Signed-off-by: Sasha Levin +--- + drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++---------- + 1 file changed, 8 insertions(+), 10 deletions(-) + +diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c +index aa25a3040f7cc..20c917327a8bd 100644 +--- a/drivers/pci/controller/dwc/pcie-qcom.c ++++ b/drivers/pci/controller/dwc/pcie-qcom.c +@@ -298,14 +298,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) + { + struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; + ++ clk_disable_unprepare(res->phy_clk); + reset_control_assert(res->pci_reset); + reset_control_assert(res->axi_reset); + reset_control_assert(res->ahb_reset); + reset_control_assert(res->por_reset); +- reset_control_assert(res->pci_reset); ++ reset_control_assert(res->phy_reset); + clk_disable_unprepare(res->iface_clk); + clk_disable_unprepare(res->core_clk); +- clk_disable_unprepare(res->phy_clk); + clk_disable_unprepare(res->aux_clk); + clk_disable_unprepare(res->ref_clk); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); +@@ -344,12 +344,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) + goto err_clk_core; + } + +- ret = clk_prepare_enable(res->phy_clk); +- if (ret) { +- dev_err(dev, "cannot prepare/enable phy clock\n"); +- goto err_clk_phy; +- } +- + ret = clk_prepare_enable(res->aux_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable aux clock\n"); +@@ -422,6 +416,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) + return ret; + } + ++ ret = clk_prepare_enable(res->phy_clk); ++ if (ret) { ++ dev_err(dev, "cannot prepare/enable phy clock\n"); ++ goto err_deassert_ahb; ++ } ++ + /* wait for clock acquisition */ + usleep_range(1000, 1500); + +@@ -439,8 +439,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) + err_clk_ref: + clk_disable_unprepare(res->aux_clk); + err_clk_aux: +- clk_disable_unprepare(res->phy_clk); +-err_clk_phy: + clk_disable_unprepare(res->core_clk); + err_clk_core: + clk_disable_unprepare(res->iface_clk); +-- +2.25.1 + diff --git a/queue-5.8/pm-devfreq-fix-the-wrong-end-with-semicolon.patch b/queue-5.8/pm-devfreq-fix-the-wrong-end-with-semicolon.patch new file mode 100644 index 00000000000..ab2879b72d9 --- /dev/null +++ b/queue-5.8/pm-devfreq-fix-the-wrong-end-with-semicolon.patch @@ -0,0 +1,38 @@ +From 20ed09e66b0e050d6772e9e50492f0b6cb2d0da0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 27 Jul 2020 11:32:31 +0900 +Subject: PM / devfreq: Fix the wrong end with semicolon + +From: Chanwoo Choi + +[ Upstream commit 27a69714450f5c9288cec2b20f1ae4f7ad34dacf ] + +Fix the wrong grammar at the end of code line by using semicolon. + +Cc: stable vger.kernel.org +Fixes: 490a421bc575 ("PM / devfreq: Add debugfs support with devfreq_summary file") +Signed-off-by: Chanwoo Choi +Signed-off-by: Sasha Levin +--- + drivers/devfreq/devfreq.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c +index 46c84dce6544a..5f8d94e812c8f 100644 +--- a/drivers/devfreq/devfreq.c ++++ b/drivers/devfreq/devfreq.c +@@ -1690,9 +1690,9 @@ static int devfreq_summary_show(struct seq_file *s, void *data) + #endif + + mutex_lock(&devfreq->lock); +- cur_freq = devfreq->previous_freq, ++ cur_freq = devfreq->previous_freq; + get_freq_range(devfreq, &min_freq, &max_freq); +- polling_ms = devfreq->profile->polling_ms, ++ polling_ms = devfreq->profile->polling_ms; + mutex_unlock(&devfreq->lock); + + seq_printf(s, +-- +2.25.1 + diff --git a/queue-5.8/series b/queue-5.8/series index 8d166334b52..ba4c59c7477 100644 --- a/queue-5.8/series +++ b/queue-5.8/series @@ -76,3 +76,9 @@ pinctrl-mediatek-fix-build-for-tristate-changes.patch efi-provide-empty-efi_enter_virtual_mode-implementat.patch arm64-fix-__cpu_logical_map-undefined-issue.patch net-openvswitch-introduce-common-code-for-flushing-f.patch +pci-qcom-add-missing-ipq806x-clocks-in-pcie-driver.patch +pci-qcom-change-duplicate-pci-reset-to-phy-reset.patch +pci-qcom-add-missing-reset-for-ipq806x.patch +pm-devfreq-fix-the-wrong-end-with-semicolon.patch +cpufreq-intel_pstate-fix-epp-setting-via-sysfs-in-ac.patch +alsa-usb-audio-add-capture-support-for-saffire-6-usb.patch