From: Jani Nikula Date: Tue, 28 May 2024 11:15:38 +0000 (+0300) Subject: drm/i915/gvt: use proper macros for DP AUX CH CTL registers X-Git-Tag: v6.11-rc1~141^2~20^2~187 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=68cc33f6137071cf634bfb3869f69accfa13eaef;p=thirdparty%2Fkernel%2Flinux.git drm/i915/gvt: use proper macros for DP AUX CH CTL registers Use the proper helpers for DP AUX CH CTL registers, instead of reinventing the wheels. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/f30d35f28ef106d6fb2faf100fe1c5e3a42dfa20.1716894909.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 840fea160aa62..06393b77a9e84 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1083,13 +1083,13 @@ static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) event = AUX_CHANNEL_A; - else if (reg == _PCH_DPB_AUX_CH_CTL || + else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) || reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) event = AUX_CHANNEL_B; - else if (reg == _PCH_DPC_AUX_CH_CTL || + else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) || reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) event = AUX_CHANNEL_C; - else if (reg == _PCH_DPD_AUX_CH_CTL || + else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) || reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) event = AUX_CHANNEL_D; else { @@ -1153,11 +1153,6 @@ static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, } } -#define _REG_HSW_DP_AUX_CH_CTL(dp) \ - ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) - -#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) - #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) #define dpy_is_valid_port(port) \ @@ -1181,12 +1176,14 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, write_vreg(vgpu, offset, p_data, bytes); data = vgpu_vreg(vgpu, offset); - if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) - && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { + if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 && + offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) { /* SKL DPB/C/D aux ctl register changed */ return 0; } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && - offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { + offset != i915_mmio_reg_offset(port_index ? + PCH_DP_AUX_CH_CTL(port_index) : + DP_AUX_CH_CTL(port_index))) { /* write to the data registers */ return 0; } @@ -2299,12 +2296,12 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) gmbus_mmio_write); MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, - dp_aux_ch_ctl_mmio_write); - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, - dp_aux_ch_ctl_mmio_write); - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, - dp_aux_ch_ctl_mmio_write); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, + dp_aux_ch_ctl_mmio_write); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, + dp_aux_ch_ctl_mmio_write); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, + dp_aux_ch_ctl_mmio_write); MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); @@ -2341,8 +2338,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, - dp_aux_ch_ctl_mmio_write); + MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL, + dp_aux_ch_ctl_mmio_write); MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 349578cc0fc85..f5c4e4e2f11f5 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -517,7 +517,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(SBI_DATA); MMIO_D(SBI_CTL_STAT); MMIO_D(PIXCLK_GATE); - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4); + MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4); MMIO_D(DDI_BUF_CTL(PORT_A)); MMIO_D(DDI_BUF_CTL(PORT_B)); MMIO_D(DDI_BUF_CTL(PORT_C)); @@ -888,9 +888,9 @@ static int iterate_pre_skl_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(FORCEWAKE_MT); MMIO_D(PCH_ADPA); - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4); - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4); - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4); MMIO_F(_MMIO(0x70440), 0xc); MMIO_F(_MMIO(0x71440), 0xc);