From: Krzysztof Kozlowski Date: Tue, 12 Feb 2019 17:50:51 +0000 (+0100) Subject: clk: samsung: exynos5410: Add gate clock for ADC X-Git-Tag: v5.2-rc1~104^2~4^4^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=691dc382769e350d4bc6f90a8edcacf7f8863d70;p=thirdparty%2Fkernel%2Flinux.git clk: samsung: exynos5410: Add gate clock for ADC Add the gate clock for ADC block on Exynos5410. Signed-off-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi Signed-off-by: Sylwester Nawrocki --- diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 0a0b09591e6fd..b2da2c8fa0c78 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), + GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0), GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",