From: Ben Widawsky Date: Thu, 15 Oct 2020 18:14:11 +0000 (-0700) Subject: pci: Disallow improper BAR registration for type 1 X-Git-Tag: v5.2.0-rc0~12^2~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=6a5b19ca63b1795011f53244f2fd9a2cf8189b72;p=thirdparty%2Fqemu.git pci: Disallow improper BAR registration for type 1 Prevent future developers working on root complexes, root ports, or bridges that also wish to implement a BAR for those, from shooting themselves in the foot. PCI type 1 headers only support 2 base address registers. It is incorrect and difficult to figure out what is wrong with the device when this mistake is made. With this, it is immediate and obvious what has gone wrong. Signed-off-by: Ben Widawsky Message-Id: <20201015181411.89104-2-ben.widawsky@intel.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- diff --git a/hw/pci/pci.c b/hw/pci/pci.c index e5b7c9a42b3..0131d9d02c1 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -1148,11 +1148,17 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, uint32_t addr; /* offset in pci config space */ uint64_t wmask; pcibus_t size = memory_region_size(memory); + uint8_t hdr_type; assert(region_num >= 0); assert(region_num < PCI_NUM_REGIONS); assert(is_power_of_2(size)); + /* A PCI bridge device (with Type 1 header) may only have at most 2 BARs */ + hdr_type = + pci_dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; + assert(hdr_type != PCI_HEADER_TYPE_BRIDGE || region_num < 2); + r = &pci_dev->io_regions[region_num]; r->addr = PCI_BAR_UNMAPPED; r->size = size;