From: Srinath Parvathaneni Date: Mon, 8 Jul 2024 15:36:42 +0000 (+0100) Subject: aarch64: Add support for sme2.1 movaz instructions. X-Git-Tag: binutils-2_43~140 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=6ab366f2643d13507e53e85684dc5b5a5e14b54b;p=thirdparty%2Fbinutils-gdb.git aarch64: Add support for sme2.1 movaz instructions. This patch adds support for following sme2.1 movaz instructions and the spec is available here [1]. 1. MOVAZ (array to vector, two registers). 2. MOVAZ (array to vector, four registers). 3. MOVAZ (tile to vector, single). [1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en --- diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index ed5ab762bc9..ceb0f34c885 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -8181,6 +8181,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SME_ZA_array_vrsh_2: case AARCH64_OPND_SME_ZA_array_vrss_2: case AARCH64_OPND_SME_ZA_array_vrsd_2: + case AARCH64_OPND_SME_ZA_ARRAY4: if (!parse_dual_indexed_reg (&str, REG_TYPE_ZATHV, &info->indexed_za, &qualifier, 0)) goto failure; diff --git a/gas/testsuite/gas/aarch64/sme2p1-3-bad.d b/gas/testsuite/gas/aarch64/sme2p1-3-bad.d new file mode 100644 index 00000000000..730d3bff752 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-3-bad.d @@ -0,0 +1,4 @@ +#name: Negative test of SME2.1 movaz array to vector instructions. +#as: -march=armv9.4-a+sme2p1 +#source: sme2p1-3-bad.s +#error_output: sme2p1-3-bad.l diff --git a/gas/testsuite/gas/aarch64/sme2p1-3-bad.l b/gas/testsuite/gas/aarch64/sme2p1-3-bad.l new file mode 100644 index 00000000000..8b7019f6163 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-3-bad.l @@ -0,0 +1,30 @@ +.*: Assembler messages: +.*: Error: operand mismatch -- `movaz {z0.s-z1.s},za.d\[w8,0,vgx2\]' +.*: Info: did you mean this\? +.*: Info: movaz {z0.d-z1.d}, za.d\[w8, 0, vgx2\] +.*: Error: operand mismatch -- `movaz {z30.h-z31.h},za.d\[w8,0,vgx2\]' +.*: Info: did you mean this\? +.*: Info: movaz {z30.d-z31.d}, za.d\[w8, 0, vgx2\] +.*: Error: operand mismatch -- `movaz {z0.b-z1.b},za.b\[w11,0,vgx2\]' +.*: Info: did you mean this\? +.*: Info: movaz {z0.d-z1.d}, za.d\[w11, 0, vgx2\] +.*: Error: expected a selection register in the range w8-w11 at operand 2 -- `movaz {z0.d-z1.d},za.d\[w13,7,vgx2\]' +.*: Error: immediate offset out of range 0 to 7 at operand 2 -- `movaz {z30.d-z31.d},za.d\[w11,15,vgx2\]' +.*: Error: invalid vector group size at operand 2 -- `movaz {z14.d-z15.d},za.d\[w9,4,vgx3\]' +.*: Error: missing immediate offset at operand 2 -- `movaz {z6.d-z7.d},za.d\[w10\]' +.*: Error: missing immediate offset at operand 2 -- `movaz {z2.d-z4.d},za.d\[w10 6\]' +.*: Error: operand mismatch -- `movaz {z0.s-z3.s},za.d\[w8,0,vgx4\]' +.*: Info: did you mean this\? +.*: Info: movaz {z0.d-z3.d}, za.d\[w8, 0, vgx4\] +.*: Error: operand mismatch -- `movaz {z28.h-z31.h},za.d\[w8,0,vgx4\]' +.*: Info: did you mean this\? +.*: Info: movaz {z28.d-z31.d}, za.d\[w8, 0, vgx4\] +.*: Error: operand mismatch -- `movaz {z0.b-z3.b},za.b\[w11,0,vgx4\]' +.*: Info: did you mean this\? +.*: Info: movaz {z0.d-z3.d}, za.d\[w11, 0, vgx4\] +.*: Error: expected a selection register in the range w8-w11 at operand 2 -- `movaz {z0.d-z3.d},za.d\[w14,7,vgx4\]' +.*: Error: invalid vector group size at operand 2 -- `movaz {z28.d-z31.d},za.d\[w11,11,vgx3\]' +.*: Error: start register out of range at operand 1 -- `movaz {z14.d-z17.d},za.d\[w9,4,vgx4\]' +.*: Error: too many registers in vector register list at operand 1 -- `movaz {z4.d-z8.d},za.d\[w10,3,vgx4\]' +.*: Error: missing immediate offset at operand 2 -- `movaz {z0.d,z3.d},za.d\[w10\]' +.*: Error: the register list must have a stride of 1 at operand 1 -- `movaz {z1.d,z4.d},za.d\[w10,20\]' diff --git a/gas/testsuite/gas/aarch64/sme2p1-3-bad.s b/gas/testsuite/gas/aarch64/sme2p1-3-bad.s new file mode 100644 index 00000000000..cec5987e535 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-3-bad.s @@ -0,0 +1,20 @@ +/* MOVAZ (array to vector, two registers). */ +movaz {z0.s - z1.s} , za.d[w8, 0, vgx2] +movaz {z30.h - z31.h} , za.d[w8, 0, vgx2] +movaz {z0.b - z1.b} , za.b[w11, 0, vgx2] +movaz {z0.d - z1.d} , za.d[w13, 7, vgx2] +movaz {z30.d - z31.d} , za.d[w11, 15, vgx2] +movaz {z14.d - z15.d} , za.d[w9, 4, vgx3] +movaz {z6.d - z7.d} , za.d[w10] +movaz {z2.d - z4.d} , za.d[w10 6] + +/* MOVAZ (array to vector, four registers). */ +movaz {z0.s - z3.s} , za.d[w8, 0, vgx4] +movaz {z28.h - z31.h} , za.d[w8, 0, vgx4] +movaz {z0.b - z3.b} , za.b[w11, 0, vgx4] +movaz {z0.d - z3.d} , za.d[w14, 7, vgx4] +movaz {z28.d - z31.d} , za.d[w11, 11, vgx3] +movaz {z14.d - z17.d} , za.d[w9, 4, vgx4] +movaz {z4.d - z8.d} , za.d[w10, 3, vgx4] +movaz {z0.d, z3.d} , za.d[w10] +movaz {z1.d, z4.d} , za.d[w10 , 20] diff --git a/gas/testsuite/gas/aarch64/sme2p1-3.d b/gas/testsuite/gas/aarch64/sme2p1-3.d new file mode 100644 index 00000000000..f9f20eb8a04 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-3.d @@ -0,0 +1,26 @@ +#name: Test of SME2.1 movaz array to vector instructions. +#as: -march=armv9.4-a+sme2p1 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: c0060a00 movaz {z0.d-z1.d}, za.d\[w8, 0, vgx2\] +.*: c0060a1e movaz {z30.d-z31.d}, za.d\[w8, 0, vgx2\] +.*: c0066a00 movaz {z0.d-z1.d}, za.d\[w11, 0, vgx2\] +.*: c0060ae0 movaz {z0.d-z1.d}, za.d\[w8, 7, vgx2\] +.*: c0066afe movaz {z30.d-z31.d}, za.d\[w11, 7, vgx2\] +.*: c0062a8e movaz {z14.d-z15.d}, za.d\[w9, 4, vgx2\] +.*: c0064a66 movaz {z6.d-z7.d}, za.d\[w10, 3, vgx2\] +.*: c0064ac2 movaz {z2.d-z3.d}, za.d\[w10, 6, vgx2\] +.*: c0060e00 movaz {z0.d-z3.d}, za.d\[w8, 0, vgx4\] +.*: c0060e1c movaz {z28.d-z31.d}, za.d\[w8, 0, vgx4\] +.*: c0066e00 movaz {z0.d-z3.d}, za.d\[w11, 0, vgx4\] +.*: c0060ee0 movaz {z0.d-z3.d}, za.d\[w8, 7, vgx4\] +.*: c0066efc movaz {z28.d-z31.d}, za.d\[w11, 7, vgx4\] +.*: c0062e8c movaz {z12.d-z15.d}, za.d\[w9, 4, vgx4\] +.*: c0064e64 movaz {z4.d-z7.d}, za.d\[w10, 3, vgx4\] +.*: c0064ec0 movaz {z0.d-z3.d}, za.d\[w10, 6, vgx4\] diff --git a/gas/testsuite/gas/aarch64/sme2p1-3.s b/gas/testsuite/gas/aarch64/sme2p1-3.s new file mode 100644 index 00000000000..3a822da478d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-3.s @@ -0,0 +1,19 @@ +/* MOVAZ (array to vector, two registers). */ +movaz {z0.d - z1.d} , za.d[w8, 0, vgx2] +movaz {z30.d - z31.d} , za.d[w8, 0, vgx2] +movaz {z0.d - z1.d} , za.d[w11, 0, vgx2] +movaz {z0.d - z1.d} , za.d[w8, 7, vgx2] +movaz {z30.d - z31.d} , za.d[w11, 7, vgx2] +movaz {z14.d - z15.d} , za.d[w9, 4, vgx2] +movaz {z6.d - z7.d} , za.d[w10, 3, vgx2] +movaz {z2.d - z3.d} , za.d[w10, 6] + +/* MOVAZ (array to vector, four registers). */ +movaz {z0.d - z3.d} , za.d[w8, 0, vgx4] +movaz {z28.d - z31.d} , za.d[w8, 0, vgx4] +movaz {z0.d - z3.d} , za.d[w11, 0, vgx4] +movaz {z0.d - z3.d} , za.d[w8, 7, vgx4] +movaz {z28.d - z31.d} , za.d[w11, 7, vgx4] +movaz {z12.d - z15.d} , za.d[w9, 4, vgx4] +movaz {z4.d - z7.d} , za.d[w10, 3, vgx4] +movaz {z0.d - z3.d} , za.d[w10, 6] diff --git a/gas/testsuite/gas/aarch64/sme2p1-4-bad.d b/gas/testsuite/gas/aarch64/sme2p1-4-bad.d new file mode 100644 index 00000000000..4656ad626b2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-4-bad.d @@ -0,0 +1,4 @@ +#name: Negative test of SME2.1 MOVAZ (tile to vector, single) instructions. +#as: -march=armv9.4-a+sme2p1 +#source: sme2p1-4-bad.s +#error_output: sme2p1-4-bad.l diff --git a/gas/testsuite/gas/aarch64/sme2p1-4-bad.l b/gas/testsuite/gas/aarch64/sme2p1-4-bad.l new file mode 100644 index 00000000000..fd35f4f2ffe --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-4-bad.l @@ -0,0 +1,76 @@ +.*: Assembler messages: +.*: Error: operand mismatch -- `movaz z0.b,za0h.s\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.b, za0h.b \[w12, 0\] +.*: Error: operand mismatch -- `movaz z31.d,za0h.b\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z31.b, za0h.b \[w12, 0\] +.*: Error: operand mismatch -- `movaz z0.b,za0v.h\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.b, za0v.b \[w12, 0\] +.*: Error: expected a ZA tile slice at operand 2 -- `movaz z0.q,za0vh.b\[w15,0\]' +.*: Error: operand mismatch -- `movaz z0.s,za0h.b\[w10,15\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.b, za0h.b \[w10, 15\] +.*: Error: ZA tile number out of range at operand 2 -- `movaz z31.b,za1v.b\[w25,15\]' +.*: Error: immediate offset out of range 0 to 15 at operand 2 -- `movaz z15.b,za0h.b\[w13,31\]' +.*: Error: missing immediate offset at operand 2 -- `movaz z7.h,za0h.b\[w14\]' +.*: Error: operand mismatch -- `movaz z0.s,za0h.h\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.h, za0h.h \[w12, 0\] +.*: Error: operand mismatch -- `movaz z31.h,za0h.d\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z31.h, za0h.h \[w12, 0\] +.*: Error: ZA tile number out of range at operand 2 -- `movaz z0.h,za1h.b\[w12,0\]' +.*: Error: expected a ZA tile slice at operand 2 -- `movaz z0.q,za0vh.h\[w12,0\]' +.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z0.h,za0h.h\[w17,0\]' +.*: Error: immediate offset out of range 0 to 15 at operand 2 -- `movaz z0.h,za0h.h\[w12,27\]' +.*: Error: ZA tile number out of range at operand 2 -- `movaz z31.h,za3v.h\[w15,7\]' +.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z15.h,za0h.h\[w2,3\]' +.*: Error: missing immediate offset at operand 2 -- `movaz z7.d,za0h.h\[w14\]' +.*: Error: operand mismatch -- `movaz z0.b,za0h.s\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.b, za0h.b \[w12, 0\] +.*: Error: operand mismatch -- `movaz z31.s,za0h.h\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z31.h, za0h.h \[w12, 0\] +.*: Error: operand mismatch -- `movaz z0.s,za3h\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.s, za3h.s \[w12, 0\] +.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z0.s,za0v.s\[w1,0\]' +.*: Error: operand mismatch -- `movaz z0.q,za0h.s\[w25,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.s, za0h.s \[w25, 0\] +.*: Error: ZA tile number out of range at operand 2 -- `movaz z31.s,za5v.s\[w15,3\]' +.*: Error: missing immediate offset at operand 2 -- `movaz z15.s,za1h.s\[w13\]' +.*: Error: operand mismatch -- `movaz z7.b,za2h.d\[w14,1\]' +.*: Info: did you mean this\? +.*: Info: movaz z7.b, za2h.b \[w14, 1\] +.*: Error: operand mismatch -- `movaz z0.b,za0h.d\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.b, za0h.b \[w12, 0\] +.*: Error: operand mismatch -- `movaz z31.d,za0h.h\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z31.h, za0h.h \[w12, 0\] +.*: Error: ZA tile number out of range at operand 2 -- `movaz z0.d,za7h.s\[w12,0\]' +.*: Error: operand mismatch -- `movaz z0.s,za0v.q\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.s, za0v.s \[w12, 0\] +.*: Error: expected a ZA tile slice at operand 2 -- `movaz z0.d,za0vh.d\[w15,0\]' +.*: Error: ZA tile number out of range at operand 2 -- `movaz z31.d,za11v.d\[w1,1\]' +.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z15.d,za3h.d\[w23,0\]' +.*: Error: missing immediate offset at operand 2 -- `movaz z7.s,za4h.q\[w14\]' +.*: Error: operand mismatch -- `movaz z0.b,za0h.q\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.b, za0h.b \[w12, 0\] +.*: Error: expected a ZA tile slice at operand 2 -- `movaz z31.q,za0vh.s\[w12,0\]' +.*: Error: ZA tile number out of range at operand 2 -- `movaz z0.q,za15h.h\[w20,0\]' +.*: Error: operand mismatch -- `movaz z0.s,za0v.d\[w12,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z0.s, za0v.s \[w12, 0\] +.*: Error: expected a selection register in the range w12-w15 at operand 2 -- `movaz z0.q,za0h.q\[w1,0\]' +.*: Error: operand mismatch -- `movaz z31.q,za15v\[w15,0\]' +.*: Info: did you mean this\? +.*: Info: movaz z31.q, za15v.q \[w15, 0\] +.*: Error: expected a ZA tile slice at operand 2 -- `movaz z5.q,za27.q\[w13,0\]' +.*: Error: missing immediate offset at operand 2 -- `movaz z7.q,za6h\[w14\]' diff --git a/gas/testsuite/gas/aarch64/sme2p1-4-bad.s b/gas/testsuite/gas/aarch64/sme2p1-4-bad.s new file mode 100644 index 00000000000..1a13191d5b2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-4-bad.s @@ -0,0 +1,48 @@ +/* MOVAZ (tile to vector, single). */ +movaz z0.b, za0h.s[w12, 0] +movaz z31.d, za0h.b[w12, 0] +movaz z0.b, za0v.h[w12, 0] +movaz z0.q, za0vh.b[w15, 0] +movaz z0.s, za0h.b[w10, 15] +movaz z31.b, za1v.b[w25, 15] +movaz z15.b, za0h.b[w13, 31] +movaz z7.h, za0h.b[w14] + +movaz z0.s, za0h.h[w12, 0] +movaz z31.h, za0h.d[w12, 0] +movaz z0.h, za1h.b[w12, 0] +movaz z0.q, za0vh.h[w12, 0] +movaz z0.h, za0h.h[w17, 0] +movaz z0.h, za0h.h[w12, 27] +movaz z31.h, za3v.h[w15, 7] +movaz z15.h, za0h.h[w2, 3] +movaz z7.d, za0h.h[w14] + +movaz z0.b, za0h.s[w12, 0] +movaz z31.s, za0h.h[w12, 0] +movaz z0.s, za3h[w12, 0] +movaz z0.s, za0v.s[w1, 0] +movaz z0.q, za0h.s[w25, 0] +movaz z0.s, za0h.s[w12, 13] +movaz z31.s, za5v.s[w15, 3] +movaz z15.s, za1h.s[w13] +movaz z7.b, za2h.d[w14, 1] + +movaz z0.b, za0h.d[w12, 0] +movaz z31.d, za0h.h[w12, 0] +movaz z0.d, za7h.s[w12, 0] +movaz z0.s, za0v.q[w12, 0] +movaz z0.d, za0vh.d[w15, 0] +movaz z0.d, za0h.d[w12, 1] +movaz z31.d, za11v.d[w1, 1] +movaz z15.d, za3h.d[w23, 0] +movaz z7.s, za4h.q[w14] + +movaz z0.b, za0h.q[w12, 0] +movaz z31.q, za0vh.s[w12, 0] +movaz z0.q, za15h.h[w20, 0] +movaz z0.s, za0v.d[w12, 0] +movaz z0.q, za0h.q[w1, 0] +movaz z31.q, za15v[w15, 0] +movaz z5.q, za27.q[w13, 0] +movaz z7.q, za6h[w14] diff --git a/gas/testsuite/gas/aarch64/sme2p1-4.d b/gas/testsuite/gas/aarch64/sme2p1-4.d new file mode 100644 index 00000000000..add27084245 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-4.d @@ -0,0 +1,53 @@ +#name: Test of SME2.1 MOVAZ (tile to vector, single) instructions. +#as: -march=armv9.4-a+sme2p1 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: c0020200 movaz z0.b, za0h.b \[w12, 0\] +.*: c002021f movaz z31.b, za0h.b \[w12, 0\] +.*: c0028200 movaz z0.b, za0v.b \[w12, 0\] +.*: c0026200 movaz z0.b, za0h.b \[w15, 0\] +.*: c00203e0 movaz z0.b, za0h.b \[w12, 15\] +.*: c002e3ff movaz z31.b, za0v.b \[w15, 15\] +.*: c002226f movaz z15.b, za0h.b \[w13, 3\] +.*: c0024227 movaz z7.b, za0h.b \[w14, 1\] +.*: c0420200 movaz z0.h, za0h.h \[w12, 0\] +.*: c042021f movaz z31.h, za0h.h \[w12, 0\] +.*: c0420300 movaz z0.h, za1h.h \[w12, 0\] +.*: c0428200 movaz z0.h, za0v.h \[w12, 0\] +.*: c0426200 movaz z0.h, za0h.h \[w15, 0\] +.*: c04202e0 movaz z0.h, za0h.h \[w12, 7\] +.*: c042e3ff movaz z31.h, za1v.h \[w15, 7\] +.*: c042226f movaz z15.h, za0h.h \[w13, 3\] +.*: c0424227 movaz z7.h, za0h.h \[w14, 1\] +.*: c0820200 movaz z0.s, za0h.s \[w12, 0\] +.*: c082021f movaz z31.s, za0h.s \[w12, 0\] +.*: c0820380 movaz z0.s, za3h.s \[w12, 0\] +.*: c0828200 movaz z0.s, za0v.s \[w12, 0\] +.*: c0826200 movaz z0.s, za0h.s \[w15, 0\] +.*: c0820260 movaz z0.s, za0h.s \[w12, 3\] +.*: c082e3ff movaz z31.s, za3v.s \[w15, 3\] +.*: c08222cf movaz z15.s, za1h.s \[w13, 2\] +.*: c0824327 movaz z7.s, za2h.s \[w14, 1\] +.*: c0c20200 movaz z0.d, za0h.d \[w12, 0\] +.*: c0c2021f movaz z31.d, za0h.d \[w12, 0\] +.*: c0c203c0 movaz z0.d, za7h.d \[w12, 0\] +.*: c0c28200 movaz z0.d, za0v.d \[w12, 0\] +.*: c0c26200 movaz z0.d, za0h.d \[w15, 0\] +.*: c0c20220 movaz z0.d, za0h.d \[w12, 1\] +.*: c0c2e3ff movaz z31.d, za7v.d \[w15, 1\] +.*: c0c222cf movaz z15.d, za3h.d \[w13, 0\] +.*: c0c24327 movaz z7.d, za4h.d \[w14, 1\] +.*: c0c30200 movaz z0.q, za0h.q \[w12, 0\] +.*: c0c3021f movaz z31.q, za0h.q \[w12, 0\] +.*: c0c303e0 movaz z0.q, za15h.q \[w12, 0\] +.*: c0c38200 movaz z0.q, za0v.q \[w12, 0\] +.*: c0c36200 movaz z0.q, za0h.q \[w15, 0\] +.*: c0c3e3ff movaz z31.q, za15v.q \[w15, 0\] +.*: c0c322ef movaz z15.q, za7h.q \[w13, 0\] +.*: c0c342c7 movaz z7.q, za6h.q \[w14, 0\] diff --git a/gas/testsuite/gas/aarch64/sme2p1-4.s b/gas/testsuite/gas/aarch64/sme2p1-4.s new file mode 100644 index 00000000000..5c48af46cb7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2p1-4.s @@ -0,0 +1,48 @@ +/* MOVAZ (tile to vector, single). */ +movaz z0.b, za0h.b[w12, 0] +movaz z31.b, za0h.b[w12, 0] +movaz z0.b, za0v.b[w12, 0] +movaz z0.b, za0h.b[w15, 0] +movaz z0.b, za0h.b[w12, 15] +movaz z31.b, za0v.b[w15, 15] +movaz z15.b, za0h.b[w13, 3] +movaz z7.b, za0h.b[w14, 1] + +movaz z0.h, za0h.h[w12, 0] +movaz z31.h, za0h.h[w12, 0] +movaz z0.h, za1h.h[w12, 0] +movaz z0.h, za0v.h[w12, 0] +movaz z0.h, za0h.h[w15, 0] +movaz z0.h, za0h.h[w12, 7] +movaz z31.h, za1v.h[w15, 7] +movaz z15.h, za0h.h[w13, 3] +movaz z7.h, za0h.h[w14, 1] + +movaz z0.s, za0h.s[w12, 0] +movaz z31.s, za0h.s[w12, 0] +movaz z0.s, za3h.s[w12, 0] +movaz z0.s, za0v.s[w12, 0] +movaz z0.s, za0h.s[w15, 0] +movaz z0.s, za0h.s[w12, 3] +movaz z31.s, za3v.s[w15, 3] +movaz z15.s, za1h.s[w13, 2] +movaz z7.s, za2h.s[w14, 1] + +movaz z0.d, za0h.d[w12, 0] +movaz z31.d, za0h.d[w12, 0] +movaz z0.d, za7h.d[w12, 0] +movaz z0.d, za0v.d[w12, 0] +movaz z0.d, za0h.d[w15, 0] +movaz z0.d, za0h.d[w12, 1] +movaz z31.d, za7v.d[w15, 1] +movaz z15.d, za3h.d[w13, 0] +movaz z7.d, za4h.d[w14, 1] + +movaz z0.q, za0h.q[w12, 0] +movaz z31.q, za0h.q[w12, 0] +movaz z0.q, za15h.q[w12, 0] +movaz z0.q, za0v.q[w12, 0] +movaz z0.q, za0h.q[w15, 0] +movaz z31.q, za15v.q[w15, 0] +movaz z15.q, za7h.q[w13, 0] +movaz z7.q, za6h.q[w14, 0] diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 64959a8c50e..5a2b99d2bc5 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -789,6 +789,7 @@ enum aarch64_opnd AARCH64_OPND_SME_ZA_array_vrsh_2, /* Tile to vector, four registers (H). */ AARCH64_OPND_SME_ZA_array_vrss_2, /* Tile to vector, four registers (S). */ AARCH64_OPND_SME_ZA_array_vrsd_2, /* Tile to vector, four registers (D). */ + AARCH64_OPND_SME_ZA_ARRAY4, /* Tile to vector, single (BHSDQ). */ AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index bfc2d8027c2..a7744681f4c 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -672,29 +672,29 @@ aarch64_insert_operand (const aarch64_operand *self, case 214: case 215: case 216: - case 225: case 226: case 227: case 228: case 229: - case 240: - case 244: - case 249: - case 257: + case 230: + case 241: + case 245: + case 250: case 258: case 259: - case 266: + case 260: case 267: case 268: case 269: - case 303: - case 307: + case 270: + case 304: + case 308: return aarch64_ins_regno (self, info, code, inst, errors); case 6: case 119: case 120: - case 313: - case 316: + case 314: + case 317: return aarch64_ins_none (self, info, code, inst, errors); case 17: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -709,17 +709,16 @@ aarch64_insert_operand (const aarch64_operand *self, case 37: case 38: case 39: - case 318: + case 319: return aarch64_ins_reglane (self, info, code, inst, errors); case 40: case 41: case 42: - case 230: case 231: - case 234: - case 270: + case 232: + case 235: case 271: - case 286: + case 272: case 287: case 288: case 289: @@ -736,12 +735,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 300: case 301: case 302: - case 304: + case 303: case 305: case 306: - case 308: + case 307: case 309: case 310: + case 311: return aarch64_ins_simple_index (self, info, code, inst, errors); case 43: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -791,14 +791,14 @@ aarch64_insert_operand (const aarch64_operand *self, case 210: case 211: case 212: - case 272: - case 311: + case 273: case 312: - case 314: + case 313: case 315: - case 317: - case 322: + case 316: + case 318: case 323: + case 324: return aarch64_ins_imm (self, info, code, inst, errors); case 52: case 53: @@ -947,7 +947,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 201: case 202: case 203: - case 285: + case 286: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); case 217: case 218: @@ -959,67 +959,69 @@ aarch64_insert_operand (const aarch64_operand *self, case 223: case 224: return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors); - case 232: + case 225: + return aarch64_ins_sme_za_tile_to_vec (self, info, code, inst, errors); case 233: - case 235: + case 234: case 236: case 237: case 238: case 239: + case 240: return aarch64_ins_sve_quad_index (self, info, code, inst, errors); - case 241: case 242: - return aarch64_ins_sve_index (self, info, code, inst, errors); case 243: - case 245: - case 265: - return aarch64_ins_sve_reglist (self, info, code, inst, errors); + return aarch64_ins_sve_index (self, info, code, inst, errors); + case 244: case 246: + case 266: + return aarch64_ins_sve_reglist (self, info, code, inst, errors); case 247: - case 250: + case 248: case 251: case 252: case 253: case 254: - case 264: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); - case 248: case 255: + case 265: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); + case 249: case 256: + case 257: return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); - case 260: - case 262: - case 273: - return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); case 261: case 263: - return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 274: + return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); + case 262: + case 264: + return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 275: case 276: case 277: case 278: case 279: case 280: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 281: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 282: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 283: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 284: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 285: return aarch64_ins_plain_shrimm (self, info, code, inst, errors); - case 319: case 320: case 321: + case 322: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); - case 324: case 325: case 326: case 327: - return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 328: + return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 329: return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index e621bd86e87..cd79ec19cdc 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1521,6 +1521,49 @@ aarch64_ins_sme_za_vrs2 (const aarch64_operand *self, return true; } +/* Encode in SME instruction such as MOVZA ZA tile slice to vector. */ +bool +aarch64_ins_sme_za_tile_to_vec (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + int fld_v = info->indexed_za.v; + int fld_rv = info->indexed_za.index.regno - 12; + int fld_zan_imm = info->indexed_za.index.imm; + int regno = info->indexed_za.regno; + + switch (info->qualifier) + { + case AARCH64_OPND_QLF_S_B: + insert_field (FLD_imm4_5, code, fld_zan_imm, 0); + break; + case AARCH64_OPND_QLF_S_H: + insert_field (FLD_ZA8_1, code, regno, 0); + insert_field (FLD_imm3_5, code, fld_zan_imm, 0); + break; + case AARCH64_OPND_QLF_S_S: + insert_field (FLD_ZA7_2, code, regno, 0); + insert_field (FLD_off2, code, fld_zan_imm, 0); + break; + case AARCH64_OPND_QLF_S_D: + insert_field (FLD_ZA6_3, code, regno, 0); + insert_field (FLD_ol, code, fld_zan_imm, 0); + break; + case AARCH64_OPND_QLF_S_Q: + insert_field (FLD_ZA5_4, code, regno, 0); + break; + default: + return false; + } + + insert_field (self->fields[0], code, fld_v, 0); + insert_field (self->fields[1], code, fld_rv, 0); + + return true; +} + /* Encode in SME instruction such as MOVA ZA tile vector register number, vector indicator, vector selector and immediate. */ bool diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index 88143eecfcd..dca0690137c 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -104,6 +104,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm); AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm); AARCH64_DECL_OPD_INSERTER (ins_sme_za_vrs1); AARCH64_DECL_OPD_INSERTER (ins_sme_za_vrs2); +AARCH64_DECL_OPD_INSERTER (ins_sme_za_tile_to_vec); AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles); AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles_range); AARCH64_DECL_OPD_INSERTER (ins_sme_za_list); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 36542af2dc4..7a7af4afea2 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -196,11 +196,66 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 19) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0x001xxxxxxxxxxxxxxxxx - mov. */ - return 2436; + if (((word >> 9) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0x001xxxxxxx0xxxxxxxxx + mov. */ + return 2436; + } + else + { + if (((word >> 16) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000000x0010xxxxxx1xxxxxxxxx + movaz. */ + return 3312; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000100x0010xxxxxx1xxxxxxxxx + movaz. */ + return 3314; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000010x0010xxxxxx1xxxxxxxxx + movaz. */ + return 3313; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000110x0010xxxxxx1xxxxxxxxx + movaz. */ + return 3315; + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0x0011xxxxxx1xxxxxxxxx + movaz. */ + return 3316; + } + } } else { @@ -216,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x000101x00xxxxxxxxxxxxxx luti4. */ - return 3413; + return 3420; } else { @@ -255,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx01101x00xxxxxxxxxxxxxx luti4. */ - return 3414; + return 3421; } else { @@ -399,7 +454,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010011x1xxxx00xxxxxxxxxx movt. */ - return 3415; + return 3422; } } else @@ -445,11 +500,22 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0xx11xxxxx10xxxxxxxxxx - mov. */ - return 2672; + if (((word >> 9) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx11xxxxx100xxxxxxxxx + mov. */ + return 2672; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx11xxxxx101xxxxxxxxx + movaz. */ + return 3310; + } } } } @@ -530,11 +596,22 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0xx11xxxxx11xxxxxxxxxx - mov. */ - return 2673; + if (((word >> 9) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx11xxxxx110xxxxxxxxx + mov. */ + return 2673; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx11xxxxx111xxxxxxxxx + movaz. */ + return 3311; + } } } } @@ -1201,7 +1278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx00xxx fmopa. */ - return 3481; + return 3488; } else { @@ -1209,7 +1286,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000000101xxxxxxxxxxxxxxxx01xxx fmopa. */ - return 3480; + return 3487; } } else @@ -1557,7 +1634,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xx0xxxxx1000xxx fmlall. */ - return 3474; + return 3481; } } } @@ -1587,7 +1664,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxxxxx1xxxxxx00xxxx fdot. */ - return 3459; + return 3466; } } else @@ -1959,7 +2036,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx0xxxxxx100xxx fmlall. */ - return 3473; + return 3480; } } } @@ -2064,7 +2141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx10xxxx fmlal. */ - return 3466; + return 3473; } } } @@ -2237,7 +2314,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxxxxx1xxxxxx11xxxx fmlal. */ - return 3465; + return 3472; } } } @@ -2279,7 +2356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010100xxxxxxxxxxxxxxxx0xxx fmlall. */ - return 3472; + return 3479; } else { @@ -2647,7 +2724,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx111xxx fdot. */ - return 3452; + return 3459; } else { @@ -2716,7 +2793,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx001xxx fdot. */ - return 3453; + return 3460; } else { @@ -2795,7 +2872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011100xxxxxxx0xxxxxxx0xxxx fmlal. */ - return 3464; + return 3471; } else { @@ -2850,7 +2927,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx0xx01xxxxx00xxxx fvdotb. */ - return 3483; + return 3490; } else { @@ -2868,7 +2945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx0xxxxxx10xxxx fdot. */ - return 3458; + return 3465; } } } @@ -2942,7 +3019,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxxxxx1xxxxxx10xxxx fvdot. */ - return 3482; + return 3489; } } } @@ -3022,7 +3099,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx01xxxxxx1xxxx fvdott. */ - return 3484; + return 3491; } else { @@ -3199,7 +3276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxx10000x fmlall. */ - return 3478; + return 3485; } else { @@ -3207,7 +3284,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxx10000x fmlall. */ - return 3479; + return 3486; } } } @@ -3262,7 +3339,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx000xxxxx00x1x fmlall. */ - return 3476; + return 3483; } else { @@ -3270,7 +3347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx000xxxxx00x1x fmlall. */ - return 3477; + return 3484; } } } @@ -3324,7 +3401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx100xxx fdot. */ - return 3462; + return 3469; } else { @@ -3332,7 +3409,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx100xxx fdot. */ - return 3463; + return 3470; } } } @@ -3394,7 +3471,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx00xx010xxxx1000xx fmlal. */ - return 3470; + return 3477; } else { @@ -3402,7 +3479,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx10xx010xxxx1000xx fmlal. */ - return 3471; + return 3478; } } } @@ -3457,7 +3534,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx010xxxxx001xx fmlal. */ - return 3468; + return 3475; } else { @@ -3465,7 +3542,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx010xxxxx001xx fmlal. */ - return 3469; + return 3476; } } } @@ -3534,7 +3611,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx001xxxxx000xx fmlall. */ - return 3475; + return 3482; } } else @@ -3617,7 +3694,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx011xxxxx00xxx fmlal. */ - return 3467; + return 3474; } } else @@ -3638,7 +3715,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x00xx111xxxxx00xxx fadd. */ - return 3416; + return 3423; } } else @@ -3657,7 +3734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x10xx111xxxxx00xxx fadd. */ - return 3417; + return 3424; } } } @@ -3783,7 +3860,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx100xxxx110xxx fdot. */ - return 3456; + return 3463; } else { @@ -3791,7 +3868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx100xxxx110xxx fdot. */ - return 3457; + return 3464; } } } @@ -4082,7 +4159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx100xxxxx01xxx fdot. */ - return 3460; + return 3467; } else { @@ -4090,7 +4167,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx100xxxxx01xxx fdot. */ - return 3461; + return 3468; } } } @@ -4361,7 +4438,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x00xx111xxxxx01xxx fsub. */ - return 3418; + return 3425; } } else @@ -4380,7 +4457,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx1x10xx111xxxxx01xxx fsub. */ - return 3419; + return 3426; } } } @@ -4442,7 +4519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx100xxxxx11xxx fdot. */ - return 3454; + return 3461; } else { @@ -4450,7 +4527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx100xxxxx11xxx fdot. */ - return 3455; + return 3462; } } } @@ -4985,7 +5062,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx101000xx1x0xxxx0 fscale. */ - return 3390; + return 3397; } } else @@ -5133,7 +5210,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x0100100111000xxxx0xxxxx fcvt. */ - return 3387; + return 3394; } else { @@ -5141,7 +5218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x1100100111000xxxx0xxxxx bfcvt. */ - return 3382; + return 3389; } } else @@ -5150,7 +5227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx110100111000xxxx0xxxxx fcvt. */ - return 3388; + return 3395; } } else @@ -5201,7 +5278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xx100111000xxxx1xxxxx fcvtn. */ - return 3389; + return 3396; } } } @@ -5284,7 +5361,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010010x110111000xxxxxxxxx0 f1cvt. */ - return 3383; + return 3390; } else { @@ -5292,7 +5369,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011010x110111000xxxxxxxxx0 f2cvt. */ - return 3384; + return 3391; } } else @@ -5303,7 +5380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110x110111000xxxxxxxxx0 bf1cvt. */ - return 3378; + return 3385; } else { @@ -5311,7 +5388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011110x110111000xxxxxxxxx0 bf2cvt. */ - return 3379; + return 3386; } } } @@ -5346,7 +5423,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001001xxx10111000xxxxxxxxx1 f1cvtl. */ - return 3385; + return 3392; } else { @@ -5354,7 +5431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxx10111000xxxxxxxxx1 f2cvtl. */ - return 3386; + return 3393; } } else @@ -5365,7 +5442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001011xxx10111000xxxxxxxxx1 bf1cvtl. */ - return 3380; + return 3387; } else { @@ -5373,7 +5450,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxx10111000xxxxxxxxx1 bf2cvtl. */ - return 3381; + return 3388; } } } @@ -5642,7 +5719,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1100xx100xxxx0 fscale. */ - return 3392; + return 3399; } } else @@ -5818,7 +5895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1010xx100xxxx0 fscale. */ - return 3391; + return 3398; } else { @@ -5826,7 +5903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1110xx100xxxx0 fscale. */ - return 3393; + return 3400; } } } @@ -10994,7 +11071,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x11010000xxxxxxx1xxxxxxxxxxxxx addpt. */ - return 3394; + return 3401; } else { @@ -11002,7 +11079,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010000xxxxxxx1xxxxxxxxxxxxx subpt. */ - return 3395; + return 3402; } } } @@ -11920,7 +11997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx0xxxxxxxxxxxxxxx maddpt. */ - return 3396; + return 3403; } else { @@ -11928,7 +12005,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxxx1011x11xxxxx1xxxxxxxxxxxxxxx msubpt. */ - return 3397; + return 3404; } } } @@ -12013,7 +12090,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000100000xxxxxxxxxxxxx addpt. */ - return 3398; + return 3405; } else { @@ -12120,7 +12197,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx000101000xxxxxxxxxxxxx subpt. */ - return 3400; + return 3407; } else { @@ -12325,7 +12402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000010xxxxxxxxxx addpt. */ - return 3399; + return 3406; } else { @@ -12366,7 +12443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx1xxxxx000011xxxxxxxxxx subpt. */ - return 3401; + return 3408; } else { @@ -14024,7 +14101,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110100xxxxxxxxxx mlapt. */ - return 3403; + return 3410; } } else @@ -14054,7 +14131,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx110110xxxxxxxxxx madpt. */ - return 3402; + return 3409; } } } @@ -14362,7 +14439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx00x100001xxxxxxxxxxxxx smaxqv. */ - return 3312; + return 3319; } else { @@ -14370,7 +14447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx01x100001xxxxxxxxxxxxx orqv. */ - return 3323; + return 3330; } } else @@ -14381,7 +14458,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx0x0101001xxxxxxxxxxxxx addqv. */ - return 3310; + return 3317; } else { @@ -14391,7 +14468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx001101001xxxxxxxxxxxxx umaxqv. */ - return 3314; + return 3321; } else { @@ -14399,7 +14476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx011101001xxxxxxxxxxxxx eorqv. */ - return 3316; + return 3323; } } } @@ -14436,7 +14513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx00x110001xxxxxxxxxxxxx sminqv. */ - return 3313; + return 3320; } else { @@ -14444,7 +14521,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx01x110001xxxxxxxxxxxxx andqv. */ - return 3311; + return 3318; } } } @@ -14464,7 +14541,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x0xx0xx111001xxxxxxxxxxxxx uminqv. */ - return 3315; + return 3322; } } } @@ -15208,7 +15285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 110001x0x00xxxxx101xxxxxxxxxxxxx ld1q. */ - return 3339; + return 3346; } else { @@ -16222,7 +16299,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x00xxxxxxxxxx zipq1. */ - return 3329; + return 3336; } else { @@ -16232,7 +16309,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111010xxxxxxxxxx uzpq1. */ - return 3327; + return 3334; } else { @@ -16240,7 +16317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111110xxxxxxxxxx tblq. */ - return 3324; + return 3331; } } } @@ -16252,7 +16329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x01xxxxxxxxxx zipq2. */ - return 3330; + return 3337; } else { @@ -16260,7 +16337,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx111x11xxxxxxxxxx uzpq2. */ - return 3328; + return 3335; } } } @@ -16740,7 +16817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0x00xxxxx000xxxxxxxxxxxxx st3q. */ - return 3348; + return 3355; } else { @@ -16750,7 +16827,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0010xxxxx000xxxxxxxxxxxxx st2q. */ - return 3347; + return 3354; } else { @@ -16758,7 +16835,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0110xxxxx000xxxxxxxxxxxxx st4q. */ - return 3349; + return 3356; } } } @@ -17205,7 +17282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0x0000101xxxxxxxxxxxxx faddqv. */ - return 3317; + return 3324; } else { @@ -17222,7 +17299,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx100101xxxxxxxxxxxxx fmaxnmqv. */ - return 3318; + return 3325; } } else @@ -17263,7 +17340,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx110101xxxxxxxxxxxxx fmaxqv. */ - return 3319; + return 3326; } } } @@ -17285,7 +17362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx101101xxxxxxxxxxxxx fminnmqv. */ - return 3320; + return 3327; } } else @@ -17304,7 +17381,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0xx0xx111101xxxxxxxxxxxxx fminqv. */ - return 3321; + return 3328; } } } @@ -17424,7 +17501,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx01xxxx111xxxxxxxxxxxxx ld2q. */ - return 3340; + return 3347; } } } @@ -17560,7 +17637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x0xx1xxxxx100xxxxxxxxxxxxx ld2q. */ - return 3343; + return 3350; } } else @@ -17705,7 +17782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x00x1xxxxx000xxxxxxxxxxxxx st2q. */ - return 3350; + return 3357; } } else @@ -17748,7 +17825,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0101xxxxx000xxxxxxxxxxxxx st3q. */ - return 3351; + return 3358; } } else @@ -17789,7 +17866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0111xxxxx000xxxxxxxxxxxxx st4q. */ - return 3352; + return 3359; } } } @@ -17818,7 +17895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0100x1xxxxxxxxxx fdot. */ - return 3439; + return 3446; } } else @@ -17827,7 +17904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0001xxxxx0101xxxxxxxxxxxx fmlalb. */ - return 3441; + return 3448; } } else @@ -17868,7 +17945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx0101xxxxxxxxxxxx fmlalt. */ - return 3451; + return 3458; } } else @@ -17901,7 +17978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xx1xxxxxxxxxx fdot. */ - return 3437; + return 3444; } } else @@ -17972,7 +18049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx100010xxxxxxxxxx fmlallbb. */ - return 3442; + return 3449; } } else @@ -17981,7 +18058,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1000x1xxxxxxxxxx fdot. */ - return 3438; + return 3445; } } else @@ -17990,7 +18067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1100xxxxxxxxxxxx fmlallbb. */ - return 3443; + return 3450; } } else @@ -17999,7 +18076,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1x01xxxxxxxxxxxx fmlallbt. */ - return 3444; + return 3451; } } else @@ -18026,7 +18103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx100010xxxxxxxxxx fmlalb. */ - return 3440; + return 3447; } } else @@ -18044,7 +18121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1100xxxxxxxxxxxx fmlalltb. */ - return 3447; + return 3454; } } else @@ -18053,7 +18130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx1x01xxxxxxxxxxxx fmlalt. */ - return 3450; + return 3457; } } else @@ -18086,7 +18163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx100xx1xxxxxxxxxx fdot. */ - return 3436; + return 3443; } } else @@ -18095,7 +18172,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx110xxxxxxxxxxxxx fmlallbt. */ - return 3445; + return 3452; } } else @@ -18127,7 +18204,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx110xxxxxxxxxxxxx fmlalltt. */ - return 3449; + return 3456; } } else @@ -18426,7 +18503,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 111001x0xx1xxxxx001xxxxxxxxxxxxx st1q. */ - return 3346; + return 3353; } } else @@ -18441,7 +18518,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1010xxxxxxxxxxxx fmlalltb. */ - return 3446; + return 3453; } else { @@ -18449,7 +18526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0001xxxxx1011xxxxxxxxxxxx fmlalltt. */ - return 3448; + return 3455; } } else @@ -19167,7 +19244,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001010x0001110xxxxxxxxxx pmov. */ - return 3331; + return 3338; } else { @@ -19175,7 +19252,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001011x0001110xxxxxxxxxx pmov. */ - return 3332; + return 3339; } } else @@ -19184,7 +19261,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x101101xx0001110xxxxxxxxxx pmov. */ - return 3333; + return 3340; } } else @@ -19193,7 +19270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x11x101xx0001110xxxxxxxxxx pmov. */ - return 3334; + return 3341; } } else @@ -19239,7 +19316,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001x10x1001110xxxxxxxxxx pmov. */ - return 3335; + return 3342; } else { @@ -19247,7 +19324,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1001x11x1001110xxxxxxxxxx pmov. */ - return 3336; + return 3343; } } else @@ -19256,7 +19333,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1011x1xx1001110xxxxxxxxxx pmov. */ - return 3337; + return 3344; } } else @@ -19265,7 +19342,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x11x1x1xx1001110xxxxxxxxxx pmov. */ - return 3338; + return 3345; } } } @@ -19284,7 +19361,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1x01xxxxx001001xxxxxxxxxx dupq. */ - return 3322; + return 3329; } else { @@ -19292,7 +19369,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1x11xxxxx001001xxxxxxxxxx extq. */ - return 3326; + return 3333; } } else @@ -19301,7 +19378,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1xx1xxxxx001101xxxxxxxxxx tbxq. */ - return 3325; + return 3332; } } else @@ -20904,7 +20981,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101100xxxxxxxxxx luti2. */ - return 3408; + return 3415; } } else @@ -20913,7 +20990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x10xxxxxxxxxx luti2. */ - return 3409; + return 3416; } } else @@ -20926,7 +21003,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101001xxxxxxxxxx luti4. */ - return 3410; + return 3417; } else { @@ -20934,7 +21011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101101xxxxxxxxxx luti4. */ - return 3411; + return 3418; } } else @@ -20943,7 +21020,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1xx1xxxxx101x11xxxxxxxxxx luti4. */ - return 3412; + return 3419; } } } @@ -21894,7 +21971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x00xxxxxxxxxx f1cvt. */ - return 3370; + return 3377; } else { @@ -21902,7 +21979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x10xxxxxxxxxx bf1cvt. */ - return 3366; + return 3373; } } else @@ -21913,7 +21990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x01xxxxxxxxxx f2cvt. */ - return 3371; + return 3378; } else { @@ -21921,7 +21998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx001000001x11xxxxxxxxxx bf2cvt. */ - return 3367; + return 3374; } } } @@ -21966,7 +22043,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x00xxxxxxxxxx fcvtn. */ - return 3375; + return 3382; } else { @@ -21974,7 +22051,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x10xxxxxxxxxx bfcvtn. */ - return 3374; + return 3381; } } else @@ -21985,7 +22062,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x01xxxxxxxxxx fcvtnb. */ - return 3376; + return 3383; } else { @@ -21993,7 +22070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1010001x11xxxxxxxxxx fcvtnt. */ - return 3377; + return 3384; } } } @@ -22054,7 +22131,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x00xxxxxxxxxx f1cvtlt. */ - return 3372; + return 3379; } else { @@ -22062,7 +22139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x10xxxxxxxxxx bf1cvtlt. */ - return 3368; + return 3375; } } else @@ -22073,7 +22150,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x01xxxxxxxxxx f2cvtlt. */ - return 3373; + return 3380; } else { @@ -22081,7 +22158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x1xx0x1001001x11xxxxxxxxxx bf2cvtlt. */ - return 3369; + return 3376; } } } @@ -23407,7 +23484,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x01xxxx111xxxxxxxxxxxxx ld3q. */ - return 3341; + return 3348; } else { @@ -23415,7 +23492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x01xxxx111xxxxxxxxxxxxx ld4q. */ - return 3342; + return 3349; } } } @@ -24588,7 +24665,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx100xxxxxxxxxxxxx ld3q. */ - return 3344; + return 3351; } else { @@ -24596,7 +24673,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx100xxxxxxxxxxxxx ld4q. */ - return 3345; + return 3352; } } else @@ -26661,7 +26738,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110100xxxxxxxx100xxxxxxxxxx luti2. */ - return 3404; + return 3411; } } } @@ -26675,7 +26752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx000xxxxxxxxxx luti4. */ - return 3406; + return 3413; } else { @@ -26683,7 +26760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxxxx100xxxxxxxxxx luti4. */ - return 3407; + return 3414; } } else @@ -26692,7 +26769,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110110xxxxxxxxx00xxxxxxxxxx luti2. */ - return 3405; + return 3412; } } } @@ -26808,7 +26885,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx10001xxxxxxxxxx fmlallbb. */ - return 3428; + return 3435; } else { @@ -26816,7 +26893,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx10001xxxxxxxxxx fmlalltb. */ - return 3430; + return 3437; } } else @@ -26827,7 +26904,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x10xxxxxx10001xxxxxxxxxx fmlallbt. */ - return 3429; + return 3436; } else { @@ -26835,7 +26912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x10xxxxxx10001xxxxxxxxxx fmlalltt. */ - return 3431; + return 3438; } } } @@ -26923,7 +27000,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110x00xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3361; + return 3368; } else { @@ -26931,7 +27008,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110x00xxxxxx11101xxxxxxxxxx fcvtn2. */ - return 3362; + return 3369; } } else @@ -26940,7 +27017,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x10xxxxxx11101xxxxxxxxxx fcvtn. */ - return 3363; + return 3370; } } } @@ -27083,7 +27160,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110x00xxxxxx11111xxxxxxxxxx fdot. */ - return 3420; + return 3427; } else { @@ -27093,7 +27170,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110010xxxxxx11111xxxxxxxxxx fdot. */ - return 3422; + return 3429; } else { @@ -27103,7 +27180,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00001110110xxxxxx11111xxxxxxxxxx fmlalb. */ - return 3424; + return 3431; } else { @@ -27111,7 +27188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01001110110xxxxxx11111xxxxxxxxxx fmlalt. */ - return 3425; + return 3432; } } } @@ -27385,7 +27462,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110110xxxxx0x1111xxxxxxxxxx fscale. */ - return 3364; + return 3371; } } } @@ -28777,7 +28854,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110001xxxx1011110xxxxxxxxxx f1cvtl. */ - return 3357; + return 3364; } else { @@ -28785,7 +28862,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110001xxxx1011110xxxxxxxxxx f1cvtl2. */ - return 3358; + return 3365; } } else @@ -28796,7 +28873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110101xxxx1011110xxxxxxxxxx bf1cvtl. */ - return 3353; + return 3360; } else { @@ -28804,7 +28881,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110101xxxx1011110xxxxxxxxxx bf1cvtl2. */ - return 3354; + return 3361; } } } @@ -28818,7 +28895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110011xxxx1011110xxxxxxxxxx f2cvtl. */ - return 3359; + return 3366; } else { @@ -28826,7 +28903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110011xxxx1011110xxxxxxxxxx f2cvtl2. */ - return 3360; + return 3367; } } else @@ -28837,7 +28914,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101110111xxxx1011110xxxxxxxxxx bf2cvtl. */ - return 3355; + return 3362; } else { @@ -28845,7 +28922,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101110111xxxx1011110xxxxxxxxxx bf2cvtl2. */ - return 3356; + return 3363; } } } @@ -30844,7 +30921,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011101x1xxxxx111111xxxxxxxxxx fscale. */ - return 3365; + return 3372; } } } @@ -32560,7 +32637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3421; + return 3428; } else { @@ -32590,7 +32667,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx0000x0xxxxxxxxxx fdot. */ - return 3423; + return 3430; } else { @@ -32600,7 +32677,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx0000x0xxxxxxxxxx fmlalb. */ - return 3426; + return 3433; } else { @@ -32608,7 +32685,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx0000x0xxxxxxxxxx fmlalt. */ - return 3427; + return 3434; } } } @@ -33150,7 +33227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x010111100xxxxxx1000x0xxxxxxxxxx fmlallbb. */ - return 3432; + return 3439; } else { @@ -33158,7 +33235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x110111100xxxxxx1000x0xxxxxxxxxx fmlalltb. */ - return 3434; + return 3441; } } else @@ -33189,7 +33266,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111x1xxxxxx1000x0xxxxxxxxxx fmlallbt. */ - return 3433; + return 3440; } else { @@ -33197,7 +33274,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111x1xxxxxx1000x0xxxxxxxxxx fmlalltt. */ - return 3435; + return 3442; } } } @@ -34670,29 +34747,29 @@ aarch64_extract_operand (const aarch64_operand *self, case 214: case 215: case 216: - case 225: case 226: case 227: case 228: case 229: - case 240: - case 244: - case 249: - case 257: + case 230: + case 241: + case 245: + case 250: case 258: case 259: - case 266: + case 260: case 267: case 268: case 269: - case 303: - case 307: + case 270: + case 304: + case 308: return aarch64_ext_regno (self, info, code, inst, errors); case 6: case 119: case 120: - case 313: - case 316: + case 314: + case 317: return aarch64_ext_none (self, info, code, inst, errors); case 11: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -34712,17 +34789,16 @@ aarch64_extract_operand (const aarch64_operand *self, case 37: case 38: case 39: - case 318: + case 319: return aarch64_ext_reglane (self, info, code, inst, errors); case 40: case 41: case 42: - case 230: case 231: - case 234: - case 270: + case 232: + case 235: case 271: - case 286: + case 272: case 287: case 288: case 289: @@ -34739,12 +34815,13 @@ aarch64_extract_operand (const aarch64_operand *self, case 300: case 301: case 302: - case 304: + case 303: case 305: case 306: - case 308: + case 307: case 309: case 310: + case 311: return aarch64_ext_simple_index (self, info, code, inst, errors); case 43: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -34795,14 +34872,14 @@ aarch64_extract_operand (const aarch64_operand *self, case 210: case 211: case 212: - case 272: - case 311: + case 273: case 312: - case 314: + case 313: case 315: - case 317: - case 322: + case 316: + case 318: case 323: + case 324: return aarch64_ext_imm (self, info, code, inst, errors); case 52: case 53: @@ -34953,7 +35030,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 201: case 202: case 203: - case 285: + case 286: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); case 217: case 218: @@ -34965,67 +35042,69 @@ aarch64_extract_operand (const aarch64_operand *self, case 223: case 224: return aarch64_ext_sme_za_vrs2 (self, info, code, inst, errors); - case 232: + case 225: + return aarch64_ext_sme_za_tile_to_vec (self, info, code, inst, errors); case 233: - case 235: + case 234: case 236: case 237: case 238: case 239: + case 240: return aarch64_ext_sve_quad_index (self, info, code, inst, errors); - case 241: case 242: - return aarch64_ext_sve_index (self, info, code, inst, errors); case 243: - case 245: - case 265: - return aarch64_ext_sve_reglist (self, info, code, inst, errors); + return aarch64_ext_sve_index (self, info, code, inst, errors); + case 244: case 246: + case 266: + return aarch64_ext_sve_reglist (self, info, code, inst, errors); case 247: - case 250: + case 248: case 251: case 252: case 253: case 254: - case 264: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); - case 248: case 255: + case 265: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); + case 249: case 256: + case 257: return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); - case 260: - case 262: - case 273: - return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); case 261: case 263: - return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 274: + return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); + case 262: + case 264: + return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 275: case 276: case 277: case 278: case 279: case 280: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 281: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 282: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 283: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 284: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 285: return aarch64_ext_plain_shrimm (self, info, code, inst, errors); - case 319: case 320: case 321: + case 322: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); - case 324: case 325: case 326: case 327: - return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); case 328: + return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors); + case 329: return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 81ebbe0bd55..6e945705319 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1956,6 +1956,55 @@ aarch64_ext_sve_float_zero_one (const aarch64_operand *self, return true; } +/* Decode SME instruction such as MOVZA ZA tile slice to vector. */ +bool +aarch64_ext_sme_za_tile_to_vec (const aarch64_operand *self, + aarch64_opnd_info *info, aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + aarch64_insn Qsize; /* fields Q:S:size. */ + int fld_v = extract_field (self->fields[0], code, 0); + int fld_rv = extract_field (self->fields[1], code, 0); + int fld_zan_imm = extract_field (FLD_imm4_5, code, 0); + + Qsize = extract_fields (inst->value, 0, 2, FLD_SME_size_22, FLD_SME_Q); + switch (Qsize) + { + case 0x0: + info->qualifier = AARCH64_OPND_QLF_S_B; + info->indexed_za.regno = 0; + info->indexed_za.index.imm = fld_zan_imm; + break; + case 0x2: + info->qualifier = AARCH64_OPND_QLF_S_H; + info->indexed_za.regno = fld_zan_imm >> 3; + info->indexed_za.index.imm = fld_zan_imm & 0x07; + break; + case 0x4: + info->qualifier = AARCH64_OPND_QLF_S_S; + info->indexed_za.regno = fld_zan_imm >> 2; + info->indexed_za.index.imm = fld_zan_imm & 0x03; + break; + case 0x6: + info->qualifier = AARCH64_OPND_QLF_S_D; + info->indexed_za.regno = fld_zan_imm >> 1; + info->indexed_za.index.imm = fld_zan_imm & 0x01; + break; + case 0x7: + info->qualifier = AARCH64_OPND_QLF_S_Q; + info->indexed_za.regno = fld_zan_imm; + break; + default: + return false; + } + + info->indexed_za.index.regno = fld_rv + 12; + info->indexed_za.v = fld_v; + + return true; +} + /* Decode ZA tile vector, vector indicator, vector selector, qualifier and immediate on numerous SME instruction fields such as MOVA. */ bool diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index a71524f9c64..2ffcef0e652 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -128,6 +128,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_vrs1); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_vrs2); +AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_tile_to_vec); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles_range); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list); diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 926b310461f..953ee11549b 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -249,6 +249,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn,FLD_ol}, "1 bit ZA tile"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_off2}, "2 bit ZA tile"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3}, "3 bit ZA tile"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_ARRAY4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv}, "ZA tile to vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 0e726102693..f65f83a0126 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -433,7 +433,11 @@ const aarch64_field fields[] = { 6, 1 }, /* ZAn: name of the bit encoded ZA tile. */ { 12, 4 }, /* opc2: in rcpc3 ld/st inst deciding the pre/post-index. */ { 30, 2 }, /* rcpc3_size: in rcpc3 ld/st, field controls Rt/Rt2 width. */ - { 5, 1 }, /* FLD_brbop: used in BRB to mean IALL or INJ. */ + { 5, 1 }, /* FLD_brbop: used in BRB to mean IALL or INJ. */ + { 8, 1 }, /* ZA8_1: name of the 1 bit encoded ZA tile ZA0-ZA1. */ + { 7, 2 }, /* ZA7_2: name of the 2 bits encoded ZA tile ZA0-ZA3. */ + { 6, 3 }, /* ZA6_3: name of the 3 bits encoded ZA tile ZA0-ZA7. */ + { 5, 4 }, /* ZA5_4: name of the 4 bits encoded ZA tile ZA0-ZA15. */ }; enum aarch64_operand_class @@ -2066,6 +2070,12 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_ZA_ARRAY4: + if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1, + get_opcode_dependent_value (opcode))) + return 0; + break; + case AARCH64_OPND_SME_ZA_array_vrss_2: case AARCH64_OPND_SME_ZA_array_vrsd_2: if (!check_za_access (opnd, mismatch_detail, idx, 12, 0, 4, @@ -4408,6 +4418,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SME_ZA_array_vrsh_2: case AARCH64_OPND_SME_ZA_array_vrss_2: case AARCH64_OPND_SME_ZA_array_vrsd_2: + case AARCH64_OPND_SME_ZA_ARRAY4: snprintf (buf, size, "%s [%s, %s%s%s]", style_reg (styler, "za%d%c%s%s", opnd->indexed_za.regno, diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 49310960305..b3ef440f98b 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -235,6 +235,10 @@ enum aarch64_field_kind FLD_opc2, FLD_rcpc3_size, FLD_brbop, + FLD_ZA8_1, + FLD_ZA7_2, + FLD_ZA6_3, + FLD_ZA5_4, }; /* Field description. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index eccfac53ad1..38be471965c 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2269,6 +2269,10 @@ QLF3(S_H,S_S,S_S), \ QLF3(S_S,S_D,S_D), \ } +#define OP_SVE_VV_D \ +{ \ + QLF2(S_D, S_D) \ +} #define OP_SVE_VV_BHS_HSD \ { \ QLF2(S_B,S_H), \ @@ -6651,6 +6655,19 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2p1_INSN ("luti4", 0xc09a4000, 0xfffe4c08, sme_size_12_bh, 0, OP3 (SME_Ztx2_STRIDED, SME_ZT0, SME_Zn_INDEX2_15), OP_SVE_VUU_BH, 0, 0), SME2p1_INSN ("luti4", 0xc09a9000, 0xfffefc0c, sme_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Zn_INDEX1_16), OP_SVE_HUU, 0, 0), + /* SME2.1 MOVAZ (array to vector, two registers). */ + SME2p1_INSN ("movaz", 0xc0060a00, 0xffff9f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_D, F_OD (2), 0), + + /* SME2.1 MOVAZ (array to vector, four registers). */ + SME2p1_INSN ("movaz", 0xc0060e00, 0xffff9f03, sme2_movaz, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_D, F_OD (4), 0), + + /* SME2.1 MOVAZ (tile to vector, single). */ + SME2p1_INSN ("movaz", 0xc0020200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_BB, 0, 0), + SME2p1_INSN ("movaz", 0xc0420200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_HH, 0, 0), + SME2p1_INSN ("movaz", 0xc0820200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_SS, 0, 0), + SME2p1_INSN ("movaz", 0xc0c20200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_DD, 0, 0), + SME2p1_INSN ("movaz", 0xc0c30200, 0xffff1e00, sme2_movaz, 0, OP2 (SVE_Zd, SME_ZA_ARRAY4), OP_SVE_QQ, 0, 0), + /* SVE2p1 Instructions. */ SVE2p1_INSN("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0), SVE2p1_INSN("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, 0), @@ -7325,6 +7342,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SME_V,FLD_SME_Rv,FLD_off2), "2 bit ZA tile") \ Y(ZA_ACCESS, sme_za_vrs2, "SME_ZA_array_vrsd_2", 0, \ F(FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3), "3 bit ZA tile") \ + Y(ZA_ACCESS, sme_za_tile_to_vec, "SME_ZA_ARRAY4", 0, \ + F(FLD_SME_V,FLD_SME_Rv), "ZA tile to vector register") \ Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \ "an SVE vector register") \ Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \