From: Dongyan Chen Date: Sat, 13 Sep 2025 02:14:35 +0000 (+0800) Subject: RISC-V: Add support for sdtrig and ssstrict extensions. X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=6affec82bd4186aaf2e6733425b1e05870fc0582;p=thirdparty%2Fbinutils-gdb.git RISC-V: Add support for sdtrig and ssstrict extensions. This implements the sdtrig extension, version 1.0[1] and ssstrict extension, version 1.0[2]. [1]https://github.com/riscv/riscv-debug-spec/blob/main/Sdtrig.adoc [2]https://github.com/riscv/riscv-profiles/issues/173 bfd/ChangeLog: * elfxx-riscv.c: Added sdtrig and ssstrict v1.0, and imply rules. gas/ChangeLog: * NEWS: Updated for sdtrig and ssstrict. * testsuite/gas/riscv/imply.d: DItto. * testsuite/gas/riscv/imply.s: Ditto. * testsuite/gas/riscv/march-help.l: Ditto. --- diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 9163712967d..085d77923a0 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1303,6 +1303,8 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvksc", "+zvks,+zvbc", check_implicit_always}, {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always}, + {"sdtrig", "+zicsr", check_implicit_always}, + {"smaia", "+ssaia", check_implicit_always}, {"smcdeleg", "+ssccfg", check_implicit_always}, {"smcsrind", "+sscsrind", check_implicit_always}, @@ -1322,6 +1324,7 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] = {"sscounterenw", "+zicsr", check_implicit_always}, {"ssctr", "+zicsr", check_implicit_always}, {"ssstateen", "+zicsr", check_implicit_always}, + {"ssstrict", "+zicsr", check_implicit_always}, {"sstc", "+zicsr", check_implicit_always}, {"sstvala", "+zicsr", check_implicit_always}, {"sstvecd", "+zicsr", check_implicit_always}, @@ -1552,6 +1555,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] = static const struct riscv_supported_ext riscv_supported_std_s_ext[] = { + {"sdtrig", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1576,6 +1580,7 @@ static const struct riscv_supported_ext riscv_supported_std_s_ext[] = {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssctr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssstrict", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/NEWS b/gas/NEWS index 5908f769fdd..b1edc04a1be 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -5,6 +5,9 @@ * NaCl target support is removed. +* Add support for RISC-V standard extensions: + sdtrig v1.0, ssstrict v1.0. + Changes in 2.45: * Add support to generate SFrame stack trace information (.sframe) diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d index c60711c7c46..9fd6102a056 100644 --- a/gas/testsuite/gas/riscv/imply.d +++ b/gas/testsuite/gas/riscv/imply.d @@ -94,6 +94,7 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sdtrig1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0 @@ -108,6 +109,7 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscounterenw1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssstateen1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssstrict1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstc1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvala1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvecd1p0 diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s index 74f28920201..6d3a7e0a52a 100644 --- a/gas/testsuite/gas/riscv/imply.s +++ b/gas/testsuite/gas/riscv/imply.s @@ -109,6 +109,8 @@ imply zvksg imply zvksc imply zvks +imply sdtrig + imply smaia imply smcdeleg imply smcsrind @@ -124,6 +126,7 @@ imply sscsrind imply sscofpmf imply sscounterenw imply ssstateen +imply ssstrict imply sstc imply sstvala imply sstvecd diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 709ccff2b7f..0ce2f896735 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -110,6 +110,7 @@ All available -march extensions for RISC-V: zcmp 1.0 zcmt 1.0 zclsd 1.0 + sdtrig 1.0 sha 1.0 shcounterenw 1.0 shgatpa 1.0 @@ -134,6 +135,7 @@ All available -march extensions for RISC-V: sscounterenw 1.0 ssctr 1.0 ssstateen 1.0 + ssstrict 1.0 sstc 1.0 sstvala 1.0 sstvecd 1.0