From: Emmanuel Blot <emmanuel.blot@sifive.com>
Date: Wed, 21 Apr 2021 13:32:36 +0000 (+0200)
Subject: target/riscv: fix a typo with interrupt names
X-Git-Tag: v6.1.0-rc0~129^2~10
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=6cfcf77573fb9714afd09b9b9ead05e002102243;p=thirdparty%2Fqemu.git

target/riscv: fix a typo with interrupt names

Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4bf6a006368..04ac03f8c91 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = {
     "vs_timer",
     "m_timer",
     "u_external",
+    "s_external",
     "vs_external",
-    "h_external",
     "m_external",
     "reserved",
     "reserved",