From: Greg Kroah-Hartman Date: Tue, 8 Aug 2023 19:18:34 +0000 (+0200) Subject: 6.4-stable patches X-Git-Tag: v4.14.322~23 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=6cfdb5ede5de3785633a57c981c5e0544ceafa16;p=thirdparty%2Fkernel%2Fstable-queue.git 6.4-stable patches added patches: drm-amdgpu-use-apt-name-for-fw-reserved-region.patch --- diff --git a/queue-6.4/drm-amdgpu-use-apt-name-for-fw-reserved-region.patch b/queue-6.4/drm-amdgpu-use-apt-name-for-fw-reserved-region.patch new file mode 100644 index 00000000000..4fca6e16c8c --- /dev/null +++ b/queue-6.4/drm-amdgpu-use-apt-name-for-fw-reserved-region.patch @@ -0,0 +1,126 @@ +From db3b5cb64a9ca301d14ed027e470834316720e42 Mon Sep 17 00:00:00 2001 +From: Lijo Lazar +Date: Fri, 24 Feb 2023 18:01:38 +0530 +Subject: drm/amdgpu: Use apt name for FW reserved region + +From: Lijo Lazar + +commit db3b5cb64a9ca301d14ed027e470834316720e42 upstream. + +Use the generic term fw_reserved_memory for FW reserve region. This +region may also hold discovery TMR in addition to other reserve +regions. This region size could be larger than discovery tmr size, hence +don't change the discovery tmr size based on this. + +Signed-off-by: Lijo Lazar +Reviewed-by: Le Ma +Signed-off-by: Alex Deucher +This change fixes reading IP discovery from debugfs. +It needed to be hand modified because GC 9.4.3 support isn't +introduced in older kernels until 228ce176434b ("drm/amdgpu: Handle +VRAM dependencies on GFXIP9.4.3") +Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2748 +Signed-off-by: Mario Limonciello +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 35 +++++++++++++++++--------------- + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +- + 2 files changed, 21 insertions(+), 17 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +@@ -1623,14 +1623,15 @@ static int amdgpu_ttm_training_reserve_v + return 0; + } + +-static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) ++static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev, ++ uint32_t reserve_size) + { + struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; + + memset(ctx, 0, sizeof(*ctx)); + + ctx->c2p_train_data_offset = +- ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); ++ ALIGN((adev->gmc.mc_vram_size - reserve_size - SZ_1M), SZ_1M); + ctx->p2c_train_data_offset = + (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); + ctx->train_data_size = +@@ -1648,9 +1649,10 @@ static void amdgpu_ttm_training_data_blo + */ + static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) + { +- int ret; + struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; + bool mem_train_support = false; ++ uint32_t reserve_size = 0; ++ int ret; + + if (!amdgpu_sriov_vf(adev)) { + if (amdgpu_atomfirmware_mem_training_supported(adev)) +@@ -1666,14 +1668,15 @@ static int amdgpu_ttm_reserve_tmr(struct + * Otherwise, fallback to legacy approach to check and reserve tmr block for ip + * discovery data and G6 memory training data respectively + */ +- adev->mman.discovery_tmr_size = +- amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); +- if (!adev->mman.discovery_tmr_size) +- adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; ++ if (adev->bios) ++ reserve_size = ++ amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); ++ if (!reserve_size) ++ reserve_size = DISCOVERY_TMR_OFFSET; + + if (mem_train_support) { + /* reserve vram for mem train according to TMR location */ +- amdgpu_ttm_training_data_block_init(adev); ++ amdgpu_ttm_training_data_block_init(adev, reserve_size); + ret = amdgpu_bo_create_kernel_at(adev, + ctx->c2p_train_data_offset, + ctx->train_data_size, +@@ -1687,14 +1690,13 @@ static int amdgpu_ttm_reserve_tmr(struct + ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; + } + +- ret = amdgpu_bo_create_kernel_at(adev, +- adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, +- adev->mman.discovery_tmr_size, +- &adev->mman.discovery_memory, +- NULL); ++ ret = amdgpu_bo_create_kernel_at( ++ adev, adev->gmc.real_vram_size - reserve_size, ++ reserve_size, &adev->mman.fw_reserved_memory, NULL); + if (ret) { + DRM_ERROR("alloc tmr failed(%d)!\n", ret); +- amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); ++ amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, ++ NULL, NULL); + return ret; + } + +@@ -1881,8 +1883,9 @@ void amdgpu_ttm_fini(struct amdgpu_devic + /* return the stolen vga memory back to VRAM */ + amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); + amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); +- /* return the IP Discovery TMR memory back to VRAM */ +- amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); ++ /* return the FW reserved memory back to VRAM */ ++ amdgpu_bo_free_kernel(&adev->mman.fw_reserved_memory, NULL, ++ NULL); + if (adev->mman.stolen_reserved_size) + amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, + NULL, NULL); +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +@@ -78,7 +78,8 @@ struct amdgpu_mman { + /* discovery */ + uint8_t *discovery_bin; + uint32_t discovery_tmr_size; +- struct amdgpu_bo *discovery_memory; ++ /* fw reserved memory */ ++ struct amdgpu_bo *fw_reserved_memory; + + /* firmware VRAM reservation */ + u64 fw_vram_usage_start_offset; diff --git a/queue-6.4/series b/queue-6.4/series index 8eab08bed69..f8e84f9f866 100644 --- a/queue-6.4/series +++ b/queue-6.4/series @@ -153,3 +153,4 @@ mtd-spi-nor-avoid-holes-in-struct-spi_mem_op.patch mtd-rawnand-fsl_upm-fix-an-off-by-one-test-in-fun_ex.patch powerpc-mm-altmap-fix-altmap-boundary-check.patch drm-imx-ipuv3-fix-front-porch-adjustment-upon-hactiv.patch +drm-amdgpu-use-apt-name-for-fw-reserved-region.patch