From: Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
Date: Tue, 16 Jul 2024 08:41:46 +0000 (+0200)
Subject: s390: Enable vcond_mask for 128-bit ops
X-Git-Tag: basepoints/gcc-16~7496
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=6d1095788e23c27061421c7d180209264ebb32f7;p=thirdparty%2Fgcc.git

s390: Enable vcond_mask for 128-bit ops

In preparation of dropping vcond{,u,eq} optabs
https://gcc.gnu.org/pipermail/gcc-patches/2024-June/654690.html
enable 128-bit operands for vcond_mask---including integer as well as
floating point.

This fixes partially PR115519 w.r.t. autovec-long-double-signaling-*.c
tests.

gcc/ChangeLog:

	* config/s390/vector.md: Enable vcond_mask for 128-bit ops.
---

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 75601172893..c8e8029167d 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -760,12 +760,12 @@
 })
 
 (define_expand "vcond_mask_<mode><tointvec>"
-  [(set (match_operand:V 0 "register_operand" "")
-	(if_then_else:V
+  [(set (match_operand:VT 0 "register_operand" "")
+	(if_then_else:VT
 	 (eq (match_operand:<TOINTVEC> 3 "register_operand" "")
 	     (match_dup 4))
-	 (match_operand:V 2 "register_operand" "")
-	 (match_operand:V 1 "register_operand" "")))]
+	 (match_operand:VT 2 "register_operand" "")
+	 (match_operand:VT 1 "register_operand" "")))]
   "TARGET_VX"
   "operands[4] = CONST0_RTX (<TOINTVEC>mode);")