From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Sun, 16 Sep 2018 12:31:53 +0000 (+0200)
Subject: 4.4-stable patches
X-Git-Tag: v4.18.9~33
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=6de0c9088bc081dc04006f840981855fa590be51;p=thirdparty%2Fkernel%2Fstable-queue.git

4.4-stable patches

added patches:
	i2c-i801-fix-dnv-s-smbctrl-register-offset.patch
	i2c-xiic-make-the-start-and-the-byte-count-write-atomic.patch
---

diff --git a/queue-4.4/i2c-i801-fix-dnv-s-smbctrl-register-offset.patch b/queue-4.4/i2c-i801-fix-dnv-s-smbctrl-register-offset.patch
new file mode 100644
index 00000000000..cbce437bd10
--- /dev/null
+++ b/queue-4.4/i2c-i801-fix-dnv-s-smbctrl-register-offset.patch
@@ -0,0 +1,47 @@
+From 851a15114895c5bce163a6f2d57e0aa4658a1be4 Mon Sep 17 00:00:00 2001
+From: Felipe Balbi <felipe.balbi@linux.intel.com>
+Date: Mon, 3 Sep 2018 11:24:57 +0300
+Subject: i2c: i801: fix DNV's SMBCTRL register offset
+
+From: Felipe Balbi <felipe.balbi@linux.intel.com>
+
+commit 851a15114895c5bce163a6f2d57e0aa4658a1be4 upstream.
+
+DNV's iTCO is slightly different with SMBCTRL sitting at a different
+offset when compared to all other devices. Let's fix so that we can
+properly use iTCO watchdog.
+
+Fixes: 84d7f2ebd70d ("i2c: i801: Add support for Intel DNV")
+Cc: <stable@vger.kernel.org> # v4.4+
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Reviewed-by: Jean Delvare <jdelvare@suse.de>
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/i2c/busses/i2c-i801.c |    7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/i2c/busses/i2c-i801.c
++++ b/drivers/i2c/busses/i2c-i801.c
+@@ -128,6 +128,7 @@
+ 
+ #define SBREG_BAR		0x10
+ #define SBREG_SMBCTRL		0xc6000c
++#define SBREG_SMBCTRL_DNV	0xcf000c
+ 
+ /* Host status bits for SMBPCISTS */
+ #define SMBPCISTS_INTS		0x08
+@@ -1251,7 +1252,11 @@ static void i801_add_tco(struct i801_pri
+ 	spin_unlock(&p2sb_spinlock);
+ 
+ 	res = &tco_res[ICH_RES_MEM_OFF];
+-	res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
++	if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
++		res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
++	else
++		res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
++
+ 	res->end = res->start + 3;
+ 	res->flags = IORESOURCE_MEM;
+ 
diff --git a/queue-4.4/i2c-xiic-make-the-start-and-the-byte-count-write-atomic.patch b/queue-4.4/i2c-xiic-make-the-start-and-the-byte-count-write-atomic.patch
new file mode 100644
index 00000000000..c97ac2ba6be
--- /dev/null
+++ b/queue-4.4/i2c-xiic-make-the-start-and-the-byte-count-write-atomic.patch
@@ -0,0 +1,59 @@
+From ae7304c3ea28a3ba47a7a8312c76c654ef24967e Mon Sep 17 00:00:00 2001
+From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+Date: Mon, 3 Sep 2018 15:11:11 +0530
+Subject: i2c: xiic: Make the start and the byte count write atomic
+
+From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+
+commit ae7304c3ea28a3ba47a7a8312c76c654ef24967e upstream.
+
+Disable interrupts while configuring the transfer and enable them back.
+
+We have below as the programming sequence
+1. start and slave address
+2. byte count and stop
+
+In some customer platform there was a lot of interrupts between 1 and 2
+and after slave address (around 7 clock cyles) if 2 is not executed
+then the transaction is nacked.
+
+To fix this case make the 2 writes atomic.
+
+Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
+Signed-off-by: Michal Simek <michal.simek@xilinx.com>
+[wsa: added a newline for better readability]
+Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
+Cc: stable@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/i2c/busses/i2c-xiic.c |    4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/i2c/busses/i2c-xiic.c
++++ b/drivers/i2c/busses/i2c-xiic.c
+@@ -533,6 +533,7 @@ static void xiic_start_recv(struct xiic_
+ {
+ 	u8 rx_watermark;
+ 	struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
++	unsigned long flags;
+ 
+ 	/* Clear and enable Rx full interrupt. */
+ 	xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
+@@ -548,6 +549,7 @@ static void xiic_start_recv(struct xiic_
+ 		rx_watermark = IIC_RX_FIFO_DEPTH;
+ 	xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
+ 
++	local_irq_save(flags);
+ 	if (!(msg->flags & I2C_M_NOSTART))
+ 		/* write the address */
+ 		xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
+@@ -558,6 +560,8 @@ static void xiic_start_recv(struct xiic_
+ 
+ 	xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
+ 		msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
++	local_irq_restore(flags);
++
+ 	if (i2c->nmsgs == 1)
+ 		/* very last, enable bus not busy as well */
+ 		xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);