From: Greg Kroah-Hartman Date: Sat, 23 Aug 2025 11:17:06 +0000 (+0200) Subject: 6.16-stable patches X-Git-Tag: v6.16.3~14 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=6de74c918907f9f933b0337ea6e71af49d2e004d;p=thirdparty%2Fkernel%2Fstable-queue.git 6.16-stable patches added patches: pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch pci-rockchip-use-standard-pcie-definitions.patch scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch --- diff --git a/queue-6.16/pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch b/queue-6.16/pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch new file mode 100644 index 0000000000..53bcf6c681 --- /dev/null +++ b/queue-6.16/pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch @@ -0,0 +1,44 @@ +From stable+bounces-172503-greg=kroah.com@vger.kernel.org Fri Aug 22 21:10:48 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 15:10:31 -0400 +Subject: PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining +To: stable@vger.kernel.org +Cc: Geraldo Nascimento , Manivannan Sadhasivam , Bjorn Helgaas , Robin Murphy , Sasha Levin +Message-ID: <20250822191032.1432952-2-sashal@kernel.org> + +From: Geraldo Nascimento + +[ Upstream commit 114b06ee108cabc82b995fbac6672230a9776936 ] + +Rockchip controllers can support up to 5.0 GT/s link speed. But the driver +doesn't set the Target Link Speed currently. This may cause failure in +retraining the link to 5.0 GT/s if supported by the endpoint. So set the +Target Link Speed to 5.0 GT/s in the Link Control and Status Register 2. + +Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") +Signed-off-by: Geraldo Nascimento +[mani: fixed whitespace warning, commit message rewording, added fixes tag] +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Tested-by: Robin Murphy +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/0afa6bc47b7f50e2e81b0b47d51c66feb0fb565f.1751322015.git.geraldogabriel@gmail.com +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/pci/controller/pcie-rockchip-host.c ++++ b/drivers/pci/controller/pcie-rockchip-host.c +@@ -342,6 +342,10 @@ static int rockchip_pcie_host_init_port( + * Enable retrain for gen2. This should be configured only after + * gen1 finished. + */ ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); ++ status &= ~PCI_EXP_LNKCTL2_TLS; ++ status |= PCI_EXP_LNKCTL2_TLS_5_0GT; ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= PCI_EXP_LNKCTL_RL; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); diff --git a/queue-6.16/pci-rockchip-use-standard-pcie-definitions.patch b/queue-6.16/pci-rockchip-use-standard-pcie-definitions.patch new file mode 100644 index 0000000000..4c8abf2137 --- /dev/null +++ b/queue-6.16/pci-rockchip-use-standard-pcie-definitions.patch @@ -0,0 +1,179 @@ +From stable+bounces-172504-greg=kroah.com@vger.kernel.org Fri Aug 22 21:10:44 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 15:10:30 -0400 +Subject: PCI: rockchip: Use standard PCIe definitions +To: stable@vger.kernel.org +Cc: Geraldo Nascimento , Bjorn Helgaas , Manivannan Sadhasivam , Sasha Levin +Message-ID: <20250822191032.1432952-1-sashal@kernel.org> + +From: Geraldo Nascimento + +[ Upstream commit cbbfe9f683f0f9b6a1da2eaa53b995a4b5961086 ] + +Current code uses custom-defined register offsets and bitfields for the +standard PCIe registers. This creates duplication as the PCI header already +defines them. So, switch to using the standard PCIe definitions and drop +the custom ones. + +Suggested-by: Bjorn Helgaas +Signed-off-by: Geraldo Nascimento +[mani: commit message rewording] +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: include bitfield.h] +Signed-off-by: Bjorn Helgaas +Link: https://patch.msgid.link/e81700ef4b49f584bc8834bfb07b6d8995fc1f42.1751322015.git.geraldogabriel@gmail.com +Stable-dep-of: 114b06ee108c ("PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-rockchip-ep.c | 4 +- + drivers/pci/controller/pcie-rockchip-host.c | 45 ++++++++++++++-------------- + drivers/pci/controller/pcie-rockchip.h | 12 ------- + 3 files changed, 26 insertions(+), 35 deletions(-) + +--- a/drivers/pci/controller/pcie-rockchip-ep.c ++++ b/drivers/pci/controller/pcie-rockchip-ep.c +@@ -518,9 +518,9 @@ static void rockchip_pcie_ep_retrain_lin + { + u32 status; + +- status = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + PCI_EXP_LNKCTL); + status |= PCI_EXP_LNKCTL_RL; +- rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_BASE + PCI_EXP_LNKCTL); + } + + static bool rockchip_pcie_ep_link_up(struct rockchip_pcie *rockchip) +--- a/drivers/pci/controller/pcie-rockchip-host.c ++++ b/drivers/pci/controller/pcie-rockchip-host.c +@@ -11,6 +11,7 @@ + * ARM PCI Host generic driver. + */ + ++#include + #include + #include + #include +@@ -40,18 +41,18 @@ static void rockchip_pcie_enable_bw_int( + { + u32 status; + +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE); +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + } + + static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) + { + u32 status; + +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + } + + static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip) +@@ -269,7 +270,7 @@ static void rockchip_pcie_set_power_limi + scale = 3; /* 0.001x */ + curr = curr / 1000; /* convert to mA */ + power = (curr * 3300) / 1000; /* milliwatt */ +- while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) { ++ while (power > FIELD_MAX(PCI_EXP_DEVCAP_PWR_VAL)) { + if (!scale) { + dev_warn(rockchip->dev, "invalid power supply\n"); + return; +@@ -278,10 +279,10 @@ static void rockchip_pcie_set_power_limi + power = power / 10; + } + +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR); +- status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) | +- (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT); +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP); ++ status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power); ++ status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_SCL, scale); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP); + } + + /** +@@ -309,14 +310,14 @@ static int rockchip_pcie_host_init_port( + rockchip_pcie_set_power_limit(rockchip); + + /* Set RC's clock architecture as common clock */ +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= PCI_EXP_LNKSTA_SLC << 16; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + + /* Set RC's RCB to 128 */ +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= PCI_EXP_LNKCTL_RCB; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + + /* Enable Gen1 training */ + rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, +@@ -341,9 +342,9 @@ static int rockchip_pcie_host_init_port( + * Enable retrain for gen2. This should be configured only after + * gen1 finished. + */ +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= PCI_EXP_LNKCTL_RL; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + + err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, + status, PCIE_LINK_IS_GEN2(status), 20, +@@ -380,15 +381,15 @@ static int rockchip_pcie_host_init_port( + + /* Clear L0s from RC's link cap */ + if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) { +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP); +- status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP); ++ status &= ~PCI_EXP_LNKCAP_ASPM_L0S; ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP); + } + +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); +- status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK; +- status |= PCIE_RC_CONFIG_DCSR_MPS_256; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCTL); ++ status &= ~PCI_EXP_DEVCTL_PAYLOAD; ++ status |= PCI_EXP_DEVCTL_PAYLOAD_256B; ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCTL); + + return 0; + err_power_off_phy: +--- a/drivers/pci/controller/pcie-rockchip.h ++++ b/drivers/pci/controller/pcie-rockchip.h +@@ -155,17 +155,7 @@ + #define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) + #define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) + #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) +-#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) +-#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 +-#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff +-#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +-#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) +-#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) +-#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) +-#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) +-#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) +-#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) +-#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) ++#define PCIE_RC_CONFIG_CR (PCIE_RC_CONFIG_BASE + 0xc0) + #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) + #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) + #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) diff --git a/queue-6.16/scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch b/queue-6.16/scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch new file mode 100644 index 0000000000..d643628dec --- /dev/null +++ b/queue-6.16/scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch @@ -0,0 +1,56 @@ +From stable+bounces-172431-greg=kroah.com@vger.kernel.org Fri Aug 22 16:46:43 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:39:31 -0400 +Subject: scsi: mpi3mr: Drop unnecessary volatile from __iomem pointers +To: stable@vger.kernel.org +Cc: Ranjan Kumar , "Martin K. Petersen" , Sasha Levin +Message-ID: <20250822143932.1267223-1-sashal@kernel.org> + +From: Ranjan Kumar + +[ Upstream commit 6853885b21cb1d7157cc14c9d30cc17141565bae ] + +The volatile qualifier is redundant for __iomem pointers. + +Cleaned up usage in mpi3mr_writeq() and sysif_regs pointer as per +Upstream compliance. + +Signed-off-by: Ranjan Kumar +Link: https://lore.kernel.org/r/20250627194539.48851-3-ranjan.kumar@broadcom.com +Signed-off-by: Martin K. Petersen +Stable-dep-of: c91e140c82eb ("scsi: mpi3mr: Serialize admin queue BAR writes on 32-bit systems") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/scsi/mpi3mr/mpi3mr.h | 2 +- + drivers/scsi/mpi3mr/mpi3mr_fw.c | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/scsi/mpi3mr/mpi3mr.h ++++ b/drivers/scsi/mpi3mr/mpi3mr.h +@@ -1185,7 +1185,7 @@ struct mpi3mr_ioc { + char name[MPI3MR_NAME_LENGTH]; + char driver_name[MPI3MR_NAME_LENGTH]; + +- volatile struct mpi3_sysif_registers __iomem *sysif_regs; ++ struct mpi3_sysif_registers __iomem *sysif_regs; + resource_size_t sysif_regs_phys; + int bars; + u64 dma_mask; +--- a/drivers/scsi/mpi3mr/mpi3mr_fw.c ++++ b/drivers/scsi/mpi3mr/mpi3mr_fw.c +@@ -23,12 +23,12 @@ module_param(poll_queues, int, 0444); + MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); + + #if defined(writeq) && defined(CONFIG_64BIT) +-static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) ++static inline void mpi3mr_writeq(__u64 b, void __iomem *addr) + { + writeq(b, addr); + } + #else +-static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) ++static inline void mpi3mr_writeq(__u64 b, void __iomem *addr) + { + __u64 data_out = b; + diff --git a/queue-6.16/scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch b/queue-6.16/scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch new file mode 100644 index 0000000000..ccd833760f --- /dev/null +++ b/queue-6.16/scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch @@ -0,0 +1,104 @@ +From stable+bounces-172432-greg=kroah.com@vger.kernel.org Fri Aug 22 16:47:13 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:39:32 -0400 +Subject: scsi: mpi3mr: Serialize admin queue BAR writes on 32-bit systems +To: stable@vger.kernel.org +Cc: Ranjan Kumar , "Martin K. Petersen" , Sasha Levin +Message-ID: <20250822143932.1267223-2-sashal@kernel.org> + +From: Ranjan Kumar + +[ Upstream commit c91e140c82eb58724c435f623702e51cc7896646 ] + +On 32-bit systems, 64-bit BAR writes to admin queue registers are +performed as two 32-bit writes. Without locking, this can cause partial +writes when accessed concurrently. + +Updated per-queue spinlocks is used to serialize these writes and prevent +race conditions. + +Fixes: 824a156633df ("scsi: mpi3mr: Base driver code") +Cc: stable@vger.kernel.org +Signed-off-by: Ranjan Kumar +Link: https://lore.kernel.org/r/20250627194539.48851-4-ranjan.kumar@broadcom.com +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/scsi/mpi3mr/mpi3mr.h | 4 ++++ + drivers/scsi/mpi3mr/mpi3mr_fw.c | 15 +++++++++++---- + drivers/scsi/mpi3mr/mpi3mr_os.c | 2 ++ + 3 files changed, 17 insertions(+), 4 deletions(-) + +--- a/drivers/scsi/mpi3mr/mpi3mr.h ++++ b/drivers/scsi/mpi3mr/mpi3mr.h +@@ -1137,6 +1137,8 @@ struct scmd_priv { + * @logdata_buf: Circular buffer to store log data entries + * @logdata_buf_idx: Index of entry in buffer to store + * @logdata_entry_sz: log data entry size ++ * @adm_req_q_bar_writeq_lock: Admin request queue lock ++ * @adm_reply_q_bar_writeq_lock: Admin reply queue lock + * @pend_large_data_sz: Counter to track pending large data + * @io_throttle_data_length: I/O size to track in 512b blocks + * @io_throttle_high: I/O size to start throttle in 512b blocks +@@ -1339,6 +1341,8 @@ struct mpi3mr_ioc { + u8 *logdata_buf; + u16 logdata_buf_idx; + u16 logdata_entry_sz; ++ spinlock_t adm_req_q_bar_writeq_lock; ++ spinlock_t adm_reply_q_bar_writeq_lock; + + atomic_t pend_large_data_sz; + u32 io_throttle_data_length; +--- a/drivers/scsi/mpi3mr/mpi3mr_fw.c ++++ b/drivers/scsi/mpi3mr/mpi3mr_fw.c +@@ -23,17 +23,22 @@ module_param(poll_queues, int, 0444); + MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); + + #if defined(writeq) && defined(CONFIG_64BIT) +-static inline void mpi3mr_writeq(__u64 b, void __iomem *addr) ++static inline void mpi3mr_writeq(__u64 b, void __iomem *addr, ++ spinlock_t *write_queue_lock) + { + writeq(b, addr); + } + #else +-static inline void mpi3mr_writeq(__u64 b, void __iomem *addr) ++static inline void mpi3mr_writeq(__u64 b, void __iomem *addr, ++ spinlock_t *write_queue_lock) + { + __u64 data_out = b; ++ unsigned long flags; + ++ spin_lock_irqsave(write_queue_lock, flags); + writel((u32)(data_out), addr); + writel((u32)(data_out >> 32), (addr + 4)); ++ spin_unlock_irqrestore(write_queue_lock, flags); + } + #endif + +@@ -2954,9 +2959,11 @@ static int mpi3mr_setup_admin_qpair(stru + (mrioc->num_admin_req); + writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries); + mpi3mr_writeq(mrioc->admin_req_dma, +- &mrioc->sysif_regs->admin_request_queue_address); ++ &mrioc->sysif_regs->admin_request_queue_address, ++ &mrioc->adm_req_q_bar_writeq_lock); + mpi3mr_writeq(mrioc->admin_reply_dma, +- &mrioc->sysif_regs->admin_reply_queue_address); ++ &mrioc->sysif_regs->admin_reply_queue_address, ++ &mrioc->adm_reply_q_bar_writeq_lock); + writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); + writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); + return retval; +--- a/drivers/scsi/mpi3mr/mpi3mr_os.c ++++ b/drivers/scsi/mpi3mr/mpi3mr_os.c +@@ -5383,6 +5383,8 @@ mpi3mr_probe(struct pci_dev *pdev, const + spin_lock_init(&mrioc->tgtdev_lock); + spin_lock_init(&mrioc->watchdog_lock); + spin_lock_init(&mrioc->chain_buf_lock); ++ spin_lock_init(&mrioc->adm_req_q_bar_writeq_lock); ++ spin_lock_init(&mrioc->adm_reply_q_bar_writeq_lock); + spin_lock_init(&mrioc->sas_node_lock); + spin_lock_init(&mrioc->trigger_lock); + diff --git a/queue-6.16/series b/queue-6.16/series index cc2be03f35..1e5f4f4c7b 100644 --- a/queue-6.16/series +++ b/queue-6.16/series @@ -270,3 +270,7 @@ drm-amd-display-fix-xorg-desktop-unresponsive-on-replay-panel.patch drm-amd-display-fix-dp-audio-dto1-clock-source-on-dce-6.patch drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs.patch drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch +scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch +scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch +pci-rockchip-use-standard-pcie-definitions.patch +pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch