From: Leon Alrae <leon.alrae@imgtec.com>
Date: Thu, 28 Jul 2016 08:28:23 +0000 (+0100)
Subject: target-mips: fix EntryHi.EHINV being cleared on TLB exception
X-Git-Tag: v2.7.0-rc1~4^2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=701074a6fc7470d0ed54e4a4bcd4d491ad8da22e;p=thirdparty%2Fqemu.git

target-mips: fix EntryHi.EHINV being cleared on TLB exception

While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---

diff --git a/target-mips/helper.c b/target-mips/helper.c
index 9fbca26d41c..c864b15b97a 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -396,6 +396,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
                        ((address >> 9) & 0x007ffff0);
     env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
+                       (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
                        (address & (TARGET_PAGE_MASK << 1));
 #if defined(TARGET_MIPS64)
     env->CP0_EntryHi &= env->SEGMask;