From: Richard Henderson Date: Fri, 4 Jul 2025 14:19:30 +0000 (-0600) Subject: target/arm: Fix PSEL size operands to tcg_gen_gvec_ands X-Git-Tag: v7.2.19~13 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=7095d415fd193a877fe727e2eec202b481a1bd73;p=thirdparty%2Fqemu.git target/arm: Fix PSEL size operands to tcg_gen_gvec_ands Gvec only operates on size 8 and multiples of 16. Predicates may be any multiple of 2. Round up the size using the appropriate function. Cc: qemu-stable@nongnu.org Fixes: 598ab0b24c0 ("target/arm: Implement PSEL") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20250704142112.1018902-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 3801c5b75ffc60957265513338e8fd5f8b6ce8a1) Signed-off-by: Michael Tokarev --- diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 02302abfbd5..a6371345f5a 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7501,6 +7501,7 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) tcg_gen_neg_i64(tmp, tmp); /* Apply to either copy the source, or write zeros. */ + pl = size_for_gvec(pl); tcg_gen_gvec_ands(MO_64, pred_full_reg_offset(s, a->pd), pred_full_reg_offset(s, a->pn), tmp, pl, pl);