From: Alistair Francis <alistair.francis@wdc.com>
Date: Tue, 30 Jun 2020 20:12:11 +0000 (-0700)
Subject: hw/riscv: Allow 64 bit access to SiFive CLINT
X-Git-Tag: v5.1.0-rc0~38^2~61
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=70b78d4e71494c90d2ccb40381336bc9b9a22f79;p=thirdparty%2Fqemu.git

hw/riscv: Allow 64 bit access to SiFive CLINT

Commit 5d971f9e672507210e77d020d89e0e89165c8fc9
"memory: Revert "memory: accept mismatching sizes in
memory_region_access_valid"" broke most RISC-V boards as they do 64 bit
accesses to the CLINT and QEMU would trigger a fault. Fix this failure
by allowing 8 byte accesses.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-Id: <122b78825b077e4dfd39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com>
---

diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index b11ffa0edc2..669c21adc2e 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -181,7 +181,7 @@ static const MemoryRegionOps sifive_clint_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN,
     .valid = {
         .min_access_size = 4,
-        .max_access_size = 4
+        .max_access_size = 8
     }
 };