From: Juzhe-Zhong Date: Tue, 19 Dec 2023 11:40:48 +0000 (+0800) Subject: RISC-V: Fix FAIL of bb-slp-cond-1.c for RVV X-Git-Tag: basepoints/gcc-15~3454 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=71bc7c6fa116dec13ca0c636c2755d26f3341b33;p=thirdparty%2Fgcc.git RISC-V: Fix FAIL of bb-slp-cond-1.c for RVV Due to recent VLSmode changes (Change for fixing ICE and run-time FAIL). The dump check is same as ARM SVE now. So adapt test for RISC-V. gcc/testsuite/ChangeLog: * gcc.dg/vect/bb-slp-cond-1.c: Adapt for RISC-V. --- diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c index 4089eb51b2e8..8faf6b6e3ace 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-cond-1.c @@ -47,6 +47,6 @@ int main () } /* { dg-final { scan-tree-dump {(no need for alias check [^\n]* when VF is 1|no alias between [^\n]* when [^\n]* is outside \(-16, 16\))} "vect" { target vect_element_align } } } */ -/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target { vect_element_align && { ! { amdgcn-*-* riscv*-*-* } } } } } } */ -/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target { amdgcn-*-* riscv*-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "loop vectorized" 1 "vect" { target { vect_element_align && { ! { amdgcn-*-* } } } } } } */ +/* { dg-final { scan-tree-dump-times "loop vectorized" 2 "vect" { target { amdgcn-*-* } } } } */