From: Weiwei Li Date: Fri, 24 Feb 2023 04:08:47 +0000 (+0800) Subject: target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions X-Git-Tag: v8.0.0-rc0~35^2~2^2~5 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=73ec0ead67ca8b4b10132b033b7388d0718b2353;p=thirdparty%2Fqemu.git target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230224040852.37109-2-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt --- diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1b0a0c1693c..b20b00a9a71 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1885,10 +1885,12 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno, static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPUConfig *cfg = &env_archcpu(env)->cfg; uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE; if (riscv_cpu_mxl(env) == MXL_RV64) { - mask |= MENVCFG_PBMTE | MENVCFG_STCE; + mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | + (cfg->ext_sstc ? MENVCFG_STCE : 0); } env->menvcfg = (env->menvcfg & ~mask) | (val & mask); @@ -1905,7 +1907,9 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, target_ulong val) { - uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE; + RISCVCPUConfig *cfg = &env_archcpu(env)->cfg; + uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | + (cfg->ext_sstc ? MENVCFG_STCE : 0); uint64_t valh = (uint64_t)val << 32; env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);