From: Iain Sandoe <iain@codesourcery.com>
Date: Sun, 29 Sep 2013 19:34:58 +0000 (+0000)
Subject: rs6000.c (rs6000_init_dwarf_reg_sizes_extra): Ensure that altivec registers are corre... 
X-Git-Tag: releases/gcc-4.9.0~3821
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=749278c58dee4d197d9cb951eb524f9159184c4c;p=thirdparty%2Fgcc.git

rs6000.c (rs6000_init_dwarf_reg_sizes_extra): Ensure that altivec registers are correctly sized on Darwin.

gcc:

	* config/rs6000/rs6000.c (rs6000_init_dwarf_reg_sizes_extra): Ensure
	that altivec registers are correctly sized on Darwin.

From-SVN: r203018
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 57edfbbd924f..543d6018f65c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-09-29  Iain Sandoe  <iain@codesourcery.com>
+
+	* config/rs6000/rs6000.c (rs6000_init_dwarf_reg_sizes_extra): Ensure
+	that altivec registers are correctly sized on Darwin.
+
 2013-09-29  Iain Sandoe  <iain@codesourcery.com>
 
 	* config/t-darwin (darwin.o, darwin-c.o, darwin-f.o,
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4197687c083e..763847c0854d 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -29050,6 +29050,27 @@ rs6000_init_dwarf_reg_sizes_extra (tree address)
 	  emit_move_insn (adjust_address (mem, mode, offset), value);
 	}
     }
+
+  if (TARGET_MACHO && ! TARGET_ALTIVEC)
+    {
+      int i;
+      enum machine_mode mode = TYPE_MODE (char_type_node);
+      rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
+      rtx mem = gen_rtx_MEM (BLKmode, addr);
+      rtx value = gen_int_mode (16, mode);
+
+      /* On Darwin, libgcc may be built to run on both G3 and G4/5.
+	 The unwinder still needs to know the size of Altivec registers.  */
+
+      for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
+	{
+	  int column = DWARF_REG_TO_UNWIND_COLUMN (i);
+	  HOST_WIDE_INT offset
+	    = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
+
+	  emit_move_insn (adjust_address (mem, mode, offset), value);
+	}
+    }
 }
 
 /* Map internal gcc register numbers to DWARF2 register numbers.  */