From: Jens Remus Date: Fri, 1 Mar 2024 11:45:14 +0000 (+0100) Subject: s390: Print base register 0 as "0" in disassembly X-Git-Tag: gdb-15-branchpoint~810 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=75a28d1a97ace81c8481fd1c85d21e6f22e68924;p=thirdparty%2Fbinutils-gdb.git s390: Print base register 0 as "0" in disassembly Base and index register 0 have no effect in address computation: "A value of zero in the B [base] or X [index] field specifies that no base or index is to be applied, and, thus, general register 0 cannot be designated as containing a base address or index." IBM z/Architecture Principles of Operation [1], chapter "Organization", section "General Registers". Index register 0 is omitted in the s390 disassembly. Base register 0 is omitted in D(B), D(L,B) and D(X,B) - the latter only if the index register is zero. To make it more apparent print base register 0 as "0" instead of "%r0", whenever it would still be printed in the disassembly. [1]: IBM z/Architecture Principles of Operation, SA22-7832-13, https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf opcodes/ * s390-dis.c: Print base register 0 as "0" in disassembly. binutils/ * NEWS: Mention base register 0 now being printed as "0" in s390 disassembly. gas/ * testsuite/gas/s390/zarch-base-index-0.d: Update test case output verification patterns to accept "0" as base base register due to disassembler output format change. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- diff --git a/binutils/NEWS b/binutils/NEWS index 7b7ac1cbba1..9c7c8f1f603 100644 --- a/binutils/NEWS +++ b/binutils/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Base register 0 is now printed as "0" instead of "%r0" in s390 disassembly. + * When objdump or readelf are used to display the contents of a .eh_frame section they will now also display the contents of the .eh_frame_hdr section, if present. diff --git a/gas/testsuite/gas/s390/zarch-base-index-0.d b/gas/testsuite/gas/s390/zarch-base-index-0.d index e6266040c8e..4dd913bff92 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0.d +++ b/gas/testsuite/gas/s390/zarch-base-index-0.d @@ -17,8 +17,8 @@ Disassembly of section .text: .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) -.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) -.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 @@ -31,46 +31,46 @@ Disassembly of section .text: .*: 5a 00 00 00 [ ]*a %r0,0 .*: 5a 00 00 00 [ ]*a %r0,0 .*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,%r0\),0 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,0\),0 .*: f3 01 10 10 20 20 [ ]*unpk 16\(1,%r1\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,%r0\),0\(2,%r0\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,0\),0\(2,0\) .*: e7 12 30 10 00 13 [ ]*vgef %v1,16\(%v2,%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 -.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 -.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index.d b/gas/testsuite/gas/s390/zarch-omitted-base-index.d index b2ff292628b..cb168a2fe18 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index.d +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index.d @@ -18,5 +18,5 @@ Disassembly of section .text: .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c index a4cba77c6ae..ee2f2cb62ed 100644 --- a/opcodes/s390-dis.c +++ b/opcodes/s390-dis.c @@ -234,8 +234,13 @@ s390_print_insn_with_opcode (bfd_vma memaddr, { info->fprintf_styled_func (info->stream, dis_style_text, "%c", separator); - info->fprintf_styled_func (info->stream, dis_style_register, - "%%r%u", val.u); + if ((flags & (S390_OPERAND_BASE | S390_OPERAND_INDEX)) + && val.u == 0) + info->fprintf_styled_func (info->stream, dis_style_register, + "%u", val.u); + else + info->fprintf_styled_func (info->stream, dis_style_register, + "%%r%u", val.u); } else if (flags & S390_OPERAND_FPR) { @@ -248,8 +253,12 @@ s390_print_insn_with_opcode (bfd_vma memaddr, { info->fprintf_styled_func (info->stream, dis_style_text, "%c", separator); - info->fprintf_styled_func (info->stream, dis_style_register, - "%%v%i", val.u); + if ((flags & S390_OPERAND_INDEX) && val.u == 0) + info->fprintf_styled_func (info->stream, dis_style_register, + "%u", val.u); + else + info->fprintf_styled_func (info->stream, dis_style_register, + "%%v%i", val.u); } else if (flags & S390_OPERAND_AR) {