From: Pratap Nirujogi <pratap.nirujogi@amd.com>
Date: Tue, 28 May 2024 19:21:44 +0000 (-0400)
Subject: drm/amd/amdgpu: Enable MMHUB prefetch for ISP v4.1.0 and 4.1.1
X-Git-Tag: v6.11-rc1~141^2~8^2~2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=75be61aa77feb09f829104fa74b359bee74f0363;p=thirdparty%2Flinux.git

drm/amd/amdgpu: Enable MMHUB prefetch for ISP v4.1.0 and 4.1.1

Remove temporary WA to disable ISP prefetch as MMHUB SAW is initialized
to support ISP HW access GART memory using the TLSi path with prefetch
enabled.

Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---

diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c
index 962da37fb1f73..aac107898baec 100644
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c
@@ -104,18 +104,6 @@ static int isp_v4_1_0_hw_init(struct amdgpu_isp *isp)
 		goto failure;
 	}
 
-	/*
-	 * Temporary WA added to disable MMHUB TLSi until the GART initialization
-	 * is ready to support MMHUB TLSi and SAW for ISP HW to access GART memory
-	 * using the TLSi path
-	 */
-	WREG32(mmDAGB0_WRCLI5_V4_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB0_WRCLI9_V4_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB0_WRCLI10_V4_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB0_WRCLI14_V4_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB0_WRCLI19_V4_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB0_WRCLI20_V4_1 >> 2, 0xFE5FEAA8);
-
 	return 0;
 
 failure:
diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h
index bd9e1f13c7481..315f2822410c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h
@@ -32,13 +32,6 @@
 
 #include "ivsrcid/isp/irqsrcs_isp_4_1.h"
 
-#define mmDAGB0_WRCLI5_V4_1	0x6811C
-#define mmDAGB0_WRCLI9_V4_1	0x6812C
-#define mmDAGB0_WRCLI10_V4_1	0x68130
-#define mmDAGB0_WRCLI14_V4_1	0x68140
-#define mmDAGB0_WRCLI19_V4_1	0x68154
-#define mmDAGB0_WRCLI20_V4_1	0x68158
-
 #define MAX_ISP410_INT_SRC 8
 
 void isp_v4_1_0_set_isp_funcs(struct amdgpu_isp *isp);
diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
index 67f95f05ecca2..4e17fa03f7b5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
@@ -104,18 +104,6 @@ static int isp_v4_1_1_hw_init(struct amdgpu_isp *isp)
 		goto failure;
 	}
 
-	/*
-	 * Temporary WA added to disable MMHUB TLSi until the GART initialization
-	 * is ready to support MMHUB TLSi and SAW for ISP HW to access GART memory
-	 * using the TLSi path
-	 */
-	WREG32(mmDAGB1_WRCLI5_V4_1_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB1_WRCLI9_V4_1_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB1_WRCLI10_V4_1_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB1_WRCLI14_V4_1_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB1_WRCLI19_V4_1_1 >> 2, 0xFE5FEAA8);
-	WREG32(mmDAGB1_WRCLI20_V4_1_1 >> 2, 0xFE5FEAA8);
-
 	return 0;
 
 failure:
diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h
index 6bfb1de191a02..dfb9522c9d6a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h
@@ -32,13 +32,6 @@
 
 #include "ivsrcid/isp/irqsrcs_isp_4_1.h"
 
-#define mmDAGB1_WRCLI5_V4_1_1   0x68420
-#define mmDAGB1_WRCLI9_V4_1_1   0x68430
-#define mmDAGB1_WRCLI10_V4_1_1  0x68434
-#define mmDAGB1_WRCLI14_V4_1_1  0x68444
-#define mmDAGB1_WRCLI19_V4_1_1  0x68458
-#define mmDAGB1_WRCLI20_V4_1_1  0x6845C
-
 #define MAX_ISP411_INT_SRC 8
 
 void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp);