From: Yash Shah <yash.shah@sifive.com>
Date: Tue, 8 Dec 2020 04:55:33 +0000 (+0530)
Subject: dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
X-Git-Tag: v5.12-rc1~19^2~69
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=75e6d7248efccc2b13d0f3811b29d3e5cb04bcad;p=thirdparty%2Fkernel%2Flinux.git

dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC

Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index c6925e0b16e46..eb6843f69f7cd 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,11 +28,17 @@ properties:
       - items:
           - enum:
               - sifive,rocket0
+              - sifive,bullet0
               - sifive,e5
+              - sifive,e7
               - sifive,e51
+              - sifive,e71
               - sifive,u54-mc
+              - sifive,u74-mc
               - sifive,u54
+              - sifive,u74
               - sifive,u5
+              - sifive,u7
           - const: riscv
       - const: riscv    # Simulator only
     description: