From: Zhenzhong Duan Date: Wed, 15 Jun 2022 03:45:01 +0000 (+0800) Subject: q35：Enable TSEG only when G_SMRAME and TSEG_EN both enabled X-Git-Tag: v7.1.0-rc0~61^2~2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=766a9814749e35b1e4537f8a6ba71ab202ce5709;p=thirdparty%2Fqemu.git q35：Enable TSEG only when G_SMRAME and TSEG_EN both enabled According to spec: "TSEG Enable (T_EN): Enabling of SMRAM memory for Extended SMRAM space only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Note that once D_LCK is set, this bit becomes read only." Changed to match the spec description. Signed-off-by: Zhenzhong Duan Message-Id: <20220615034501.2733802-1-zhenzhong.duan@intel.com> Signed-off-by: Paolo Bonzini --- diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index ab5a47aff56..20da1213747 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -379,7 +379,8 @@ static void mch_update_smram(MCHPCIState *mch) memory_region_set_enabled(&mch->high_smram, false); } - if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { + if ((pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) && + (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME)) { switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: