From: Conor Dooley Date: Sun, 23 Nov 2025 18:53:42 +0000 (+0000) Subject: MAINTAINERS: add tree to RISC-V Microchip entry X-Git-Tag: v6.19-rc1~100^2~1^2~8 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=76cc0ba2af91c88d36adb4d0a3d5529726353051;p=thirdparty%2Flinux.git MAINTAINERS: add tree to RISC-V Microchip entry In fairness to my own employer, lumping it in as "misc" is not quite accurate when they do pay me to look after the platform. Move the tree link for it to its entry, rather than having the RISC-V MISC SOC SUPPORT entry cover it. Signed-off-by: Conor Dooley --- diff --git a/MAINTAINERS b/MAINTAINERS index 7309a0c685351..4981224985b4f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22084,6 +22084,7 @@ M: Conor Dooley M: Daire McNamara L: linux-riscv@lists.infradead.org S: Supported +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ (dts, soc, firmware) F: Documentation/devicetree/bindings/clock/microchip,mpfs*.yaml F: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml @@ -22117,7 +22118,6 @@ L: linux-riscv@lists.infradead.org S: Maintained T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: arch/riscv/boot/dts/canaan/ -F: arch/riscv/boot/dts/microchip/ F: arch/riscv/boot/dts/sifive/ RISC-V PMU DRIVERS