From: Sergey Sorokin Date: Mon, 7 Sep 2015 09:39:30 +0000 (+0100) Subject: target-arm: Fix arm_excp_unmasked() function X-Git-Tag: v2.5.0-rc0~153^2~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=771842585f3119f69641ed90a97d56eb9ed6f5ae;p=thirdparty%2Fqemu.git target-arm: Fix arm_excp_unmasked() function There is an error in arm_excp_unmasked() function: bitwise operator & is used with integer and bool operands causing an incorrect zeroed result. The patch fixes it. Signed-off-by: Sergey Sorokin Message-id: 1441209238-16881-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c794afcdbff..4bd5dc875c5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1520,8 +1520,8 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, CPUARMState *env = cs->env_ptr; unsigned int cur_el = arm_current_el(env); bool secure = arm_is_secure(env); - uint32_t scr; - uint32_t hcr; + bool scr; + bool hcr; bool pstate_unmasked; int8_t unmasked = 0; @@ -1548,7 +1548,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, * set then FIQs can be masked by CPSR.F when non-secure but only * when FIQs are only routed to EL3. */ - scr &= !((env->cp15.scr_el3 & SCR_FW) && !hcr); + scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); pstate_unmasked = !(env->daif & PSTATE_F); break;