From: Igor Zamyatin <igor.zamyatin@intel.com>
Date: Tue, 11 Jun 2013 09:40:26 +0000 (+0000)
Subject: invoke.texi (core-avx2): Document.
X-Git-Tag: releases/gcc-4.9.0~5456
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=77cea46edbb0b526aa04e4bee9be85103de60fb2;p=thirdparty%2Fgcc.git

invoke.texi (core-avx2): Document.

        * doc/invoke.texi (core-avx2): Document.
        (slm): Likewise.
        (atom): Updated with MOVBE.

From-SVN: r199943
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3c881b0cf974..52f7e7cf5375 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2013-06-11  Igor Zamyatin  <igor.zamyatin@intel.com>
+
+	* doc/invoke.texi (core-avx2): Document.
+	(slm): Likewise.
+	(atom): Updated with MOVBE.
+
 2013-06-11  Richard Biener  <rguenther@suse.de>
 
 	* collect2.c (main): Do not redirect ld stdout/stderr when
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b7b32f73b75b..dd828800955c 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13833,10 +13833,19 @@ Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
 SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction
 set support.
 
+@item core-avx2
+Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2
+and F16C instruction set support.
+
 @item atom
-Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
+Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
 instruction set support.
 
+@item slm
+Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1 and SSE4.2 instruction set support.
+
 @item k6
 AMD K6 CPU with MMX instruction set support.